^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***********************license start***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Author: Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Contact: support@caviumnetworks.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the OCTEON SDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003-2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License, Version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NONINFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this file; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * or visit http://www.gnu.org/licenses/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file may also be available under a different license from Cavium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Contact Cavium Networks for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ***********************license end**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Utility functions to decode Octeon's RSL_INT_BLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * interrupts into error messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/octeon/cvmx-asxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/octeon/cvmx-gmxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef PRINT_ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PRINT_ERROR(format, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * CN58XX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @block: Interface to enable 0-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __cvmx_interrupt_asxx_enable(int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) union cvmx_asxx_int_en csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * CN38XX and CN58XX have two interfaces with 4 ports per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * interface. All other chips have a max of 3 ports on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * interface 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mask = 0xf; /* Set enables for 4 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mask = 0x7; /* Set enables for 3 ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Enable interface interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) csr.s.txpsh = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) csr.s.txpop = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) csr.s.ovrflw = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Enable GMX error reporting for the supplied interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @interface: Interface to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __cvmx_interrupt_gmxx_enable(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) union cvmx_gmxx_inf_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) union cvmx_gmxx_tx_int_en gmx_tx_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (mode.s.en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (mode.cn52xx.mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 1: /* XAUI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) num_ports = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 2: /* SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case 3: /* PICMG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) num_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) default: /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) num_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) num_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (mode.s.en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (OCTEON_IS_MODEL(OCTEON_CN38XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * SPI on CN38XX and CN58XX report all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * errors through port 0. RGMII needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * to check all 4 ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (mode.s.type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) num_ports = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) num_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * CN30XX, CN31XX, and CN50XX have two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * or three ports. GMII and MII has 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * RGMII has three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (mode.s.type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) num_ports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) num_ports = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) num_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) gmx_tx_int_en.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (num_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (OCTEON_IS_MODEL(OCTEON_CN38XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) || OCTEON_IS_MODEL(OCTEON_CN58XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) gmx_tx_int_en.cn38xx.ncb_nxa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) gmx_tx_int_en.s.pko_nxa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (index = 0; index < num_ports; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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