^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***********************license start***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Author: Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Contact: support@caviumnetworks.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the OCTEON SDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003-2018 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License, Version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NONINFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this file; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * or visit http://www.gnu.org/licenses/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file may also be available under a different license from Cavium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Contact Cavium Networks for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ***********************license end**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Functions for XAUI initialization, configuration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * and monitoring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/octeon/cvmx-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/octeon/cvmx-helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/octeon/cvmx-pko-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/octeon/cvmx-gmxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/octeon/cvmx-pcsx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/octeon/cvmx-pcsxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int __cvmx_helper_xaui_enumerate(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) union cvmx_gmxx_hg2_control gmx_hg2_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (gmx_hg2_control.s.hg2tx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Probe a XAUI interface and determine the number of ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * connected to it. The XAUI interface should still be down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * after this call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @interface: Interface to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Returns Number of ports on the interface. Zero to disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int __cvmx_helper_xaui_probe(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) union cvmx_gmxx_inf_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * interface needs to be enabled before IPD otherwise per port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * backpressure may not work properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mode.s.en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __cvmx_helper_setup_gmx(interface, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Setup PKO to support 16 ports for HiGig2 virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * ports. We're pointing all of the PKO packet ports for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * interface to the XAUI. This allows us to use HiGig2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * backpressure per port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pko_mem_port_ptrs.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * We set each PKO port to have equal priority in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * round robin fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pko_mem_port_ptrs.s.static_p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pko_mem_port_ptrs.s.qos_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* All PKO ports map to the same XAUI hardware port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pko_mem_port_ptrs.s.eid = interface * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pko_mem_port_ptrs.s.pid = interface * 16 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return __cvmx_helper_xaui_enumerate(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Bringup and enable a XAUI interface. After this call packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * I/O should be fully functional. This is called with IPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * enabled but PKO disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @interface: Interface to bring up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int __cvmx_helper_xaui_enable(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) union cvmx_gmxx_prtx_cfg gmx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) union cvmx_pcsxx_control1_reg xauiCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) union cvmx_gmxx_tx_int_en gmx_tx_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Setup PKND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* (1) Interface has already been enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* (2) Disable GMX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) xauiMiscCtl.s.gmxeno = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* (3) Disable GMX and PCSX interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* (4) Bring up the PCSX and GMX reconciliation layer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* (4)a Set polarity and lane swapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* (4)b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Enable better IFG packing and improves performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gmxXauiTxCtl.s.dic_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gmxXauiTxCtl.s.uni_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* (4)c Aply reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) xauiCtl.s.lo_pwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Issuing a reset here seems to hang some CN68XX chips. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) xauiCtl.s.reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Wait for PCS to come out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reset, ==, 0, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Wait for PCS to be aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (CVMX_PCSXX_10GBX_STATUS_REG(interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Wait for RX to be ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) status, ==, 0, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* (6) Configure GMX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gmx_cfg.s.en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Wait for GMX RX to be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rx_idle, ==, 1, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Wait for GMX TX to be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tx_idle, ==, 1, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* GMX configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) gmx_cfg.s.speed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gmx_cfg.s.speed_msb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) gmx_cfg.s.slottime = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* (7) Clear out any error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Wait for receive link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rcv_lnk, ==, 1, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) xmtflt, ==, 0, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rcvflt, ==, 0, 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* (8) Enable packet reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) xauiMiscCtl.s.gmxeno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) gmx_cfg.s.en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __cvmx_interrupt_gmxx_enable(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Return the link state of an IPD/PKO port as returned by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * auto negotiation. The result of this function may not match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Octeon's link config if auto negotiation has changed since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * the last call to cvmx_helper_link_set().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @ipd_port: IPD/PKO port to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Returns Link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) union cvmx_helper_link_info __cvmx_helper_xaui_link_get(int ipd_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int interface = cvmx_helper_get_interface_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) union cvmx_helper_link_info result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pcsxx_status1_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Only return a link if both RX and TX are happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (pcsxx_status1_reg.s.rcv_lnk == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) result.s.link_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) result.s.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) result.s.speed = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Disable GMX and PCSX interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Configure an IPD/PKO port for the specified link state. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * function does not influence auto negotiation at the PHY level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * The passed link state must always match the link state returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * by cvmx_helper_link_get().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @ipd_port: IPD/PKO port to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @link_info: The new link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int __cvmx_helper_xaui_link_set(int ipd_port, union cvmx_helper_link_info link_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int interface = cvmx_helper_get_interface_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* If the link shouldn't be up, then just return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!link_info.s.link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Do nothing if both RX and TX are happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Bring the link up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return __cvmx_helper_xaui_enable(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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