^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***********************license start***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Author: Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Contact: support@caviumnetworks.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the OCTEON SDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003-2018 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License, Version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NONINFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this file; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * or visit http://www.gnu.org/licenses/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file may also be available under a different license from Cavium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Contact Cavium Networks for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ***********************license end**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Functions for SGMII initialization, configuration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * and monitoring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/octeon/cvmx-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/octeon/cvmx-helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/octeon/cvmx-helper-board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/octeon/cvmx-gmxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/octeon/cvmx-pcsx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/octeon/cvmx-pcsxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Perform initialization required only once for an SGMII port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @interface: Interface to init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @index: Index of prot on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Disable GMX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) gmxx_prtx_cfg.s.en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * appropriate value. 1000BASE-X specifies a 10ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * interval. SGMII specifies a 1.6ms interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pcs_misc_ctl_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pcsx_linkx_timer_count_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (pcs_misc_ctl_reg.s.mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* 1000BASE-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pcsx_linkx_timer_count_reg.s.count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (10000ull * clock_mhz) >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pcsx_linkx_timer_count_reg.s.count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (1600ull * clock_mhz) >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pcsx_linkx_timer_count_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Write the advertisement register to be used as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * tx_Config_Reg<D15:D0> of the autonegotiation. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * In SGMII PHY mode, tx_Config_Reg<D15:D0> is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * tx_Config_Reg<D15:D0> is the fixed value 0x4001, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * step can be skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (pcs_misc_ctl_reg.s.mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* 1000BASE-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pcsx_anx_adv_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pcsx_anx_adv_reg.s.rem_flt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pcsx_anx_adv_reg.s.pause = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pcsx_anx_adv_reg.s.hfd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pcsx_anx_adv_reg.s.fd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pcsx_anx_adv_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pcsx_miscx_ctl_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (pcsx_miscx_ctl_reg.s.mac_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* PHY Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pcsx_sgmx_an_adv_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pcsx_sgmx_an_adv_reg.s.link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pcsx_sgmx_an_adv_reg.s.dup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pcsx_sgmx_an_adv_reg.s.speed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pcsx_sgmx_an_adv_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* MAC Mode - Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Initialize the SERTES link for the first time or after a loss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * of link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @interface: Interface to init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @index: Index of prot on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) union cvmx_pcsx_mrx_control_reg control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Take PCS through a reset sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * value of the other PCS*_MR*_CONTROL_REG bits). Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * PCS*_MR*_CONTROL_REG[RESET] until it changes value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) control_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) control_reg.s.reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) control_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (CVMX_PCSX_MRX_CONTROL_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cvmx_dprintf("SGMII%d: Timeout waiting for port %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "to finish reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) interface, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * sgmii negotiation starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) control_reg.s.rst_an = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) control_reg.s.an_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) control_reg.s.pwr_dn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) control_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * that sgmii autonegotiation is complete. In MAC mode this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * isn't an ethernet link, but a link between Octeon and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Configure an SGMII link to the specified speed after the SERTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * link is up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @interface: Interface to init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @index: Index of prot on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @link_info: Link state to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) union cvmx_helper_link_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) link_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Disable GMX before we make any changes. Remember the enable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) is_enabled = gmxx_prtx_cfg.s.en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gmxx_prtx_cfg.s.en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Wait for GMX to be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (CVMX_WAIT_FOR_FIELD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rx_idle, ==, 1, 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cvmx_dprintf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ("SGMII%d: Timeout waiting for port %d to be idle\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) interface, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Read GMX CFG again to make sure the disable completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Get the misc control for PCS. We will need to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * duplication amount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pcsx_miscx_ctl_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Use GMXENO to force the link down if the status we get says
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * it should be down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Only change the duplex setting if the link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (link_info.s.link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Do speed based setting for GMX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) switch (link_info.s.speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) gmxx_prtx_cfg.s.speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) gmxx_prtx_cfg.s.speed_msb = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gmxx_prtx_cfg.s.slottime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Setting from GMX-603 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pcsx_miscx_ctl_reg.s.samp_pt = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gmxx_prtx_cfg.s.speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) gmxx_prtx_cfg.s.speed_msb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) gmxx_prtx_cfg.s.slottime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pcsx_miscx_ctl_reg.s.samp_pt = 0x5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) gmxx_prtx_cfg.s.speed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gmxx_prtx_cfg.s.speed_msb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) gmxx_prtx_cfg.s.slottime = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pcsx_miscx_ctl_reg.s.samp_pt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Write the new misc control for PCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pcsx_miscx_ctl_reg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Write the new GMX settings with the port still disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Read GMX CFG again to make sure the config completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Restore the enabled / disabled state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) gmxx_prtx_cfg.s.en = is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Bring up the SGMII interface to be ready for packet I/O but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * leave I/O disabled using the GMX override. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * follows the bringup documented in 10.6.3 of the manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @interface: Interface to bringup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @num_ports: Number of ports on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __cvmx_helper_setup_gmx(interface, num_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (index = 0; index < num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int ipd_port = cvmx_helper_get_ipd_port(interface, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Linux kernel driver will call ....link_set with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * proper link state. In the simulator there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * link state polling and hence it is set from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __cvmx_helper_sgmii_link_set(ipd_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __cvmx_helper_sgmii_link_get(ipd_port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int __cvmx_helper_sgmii_enumerate(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Probe a SGMII interface and determine the number of ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * connected to it. The SGMII interface should still be down after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * this call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @interface: Interface to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Returns Number of ports on the interface. Zero to disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int __cvmx_helper_sgmii_probe(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) union cvmx_gmxx_inf_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * interface needs to be enabled before IPD otherwise per port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * backpressure may not work properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mode.s.en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return __cvmx_helper_sgmii_enumerate(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Bringup and enable a SGMII interface. After this call packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * I/O should be fully functional. This is called with IPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * enabled but PKO disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @interface: Interface to bring up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int __cvmx_helper_sgmii_enable(int interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int num_ports = cvmx_helper_ports_on_interface(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __cvmx_helper_sgmii_hardware_init(interface, num_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (index = 0; index < num_ports; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gmxx_prtx_cfg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gmxx_prtx_cfg.s.en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) gmxx_prtx_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __cvmx_interrupt_gmxx_enable(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Return the link state of an IPD/PKO port as returned by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * auto negotiation. The result of this function may not match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Octeon's link config if auto negotiation has changed since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * the last call to cvmx_helper_link_set().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @ipd_port: IPD/PKO port to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Returns Link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) union cvmx_helper_link_info result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int interface = cvmx_helper_get_interface_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int index = cvmx_helper_get_interface_index_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* The simulator gives you a simulated 1Gbps full duplex link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) result.s.link_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) result.s.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) result.s.speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pcsx_mrx_control_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (pcsx_mrx_control_reg.s.loopbck1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Force 1Gbps full duplex link for internal loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) result.s.link_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) result.s.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) result.s.speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pcs_misc_ctl_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (pcs_misc_ctl_reg.s.mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* 1000BASE-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pcsx_miscx_ctl_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (pcsx_miscx_ctl_reg.s.mac_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* PHY Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Don't bother continuing if the SERTES low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * level link is down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pcsx_mrx_status_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) (index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (pcsx_mrx_status_reg.s.lnk_st == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (__cvmx_helper_sgmii_hardware_init_link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (interface, index) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Read the autoneg results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pcsx_anx_results_reg.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (pcsx_anx_results_reg.s.an_cpt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Auto negotiation is complete. Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * status accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) result.s.full_duplex =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pcsx_anx_results_reg.s.dup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) result.s.link_up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pcsx_anx_results_reg.s.link_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) switch (pcsx_anx_results_reg.s.spd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) result.s.speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) result.s.speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) result.s.speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) result.s.speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) result.s.link_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Auto negotiation isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * complete. Return link down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) result.s.speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) result.s.link_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else { /* MAC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) result = __cvmx_helper_board_link_get(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Configure an IPD/PKO port for the specified link state. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * function does not influence auto negotiation at the PHY level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * The passed link state must always match the link state returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * by cvmx_helper_link_get().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @ipd_port: IPD/PKO port to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @link_info: The new link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Returns Zero on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int __cvmx_helper_sgmii_link_set(int ipd_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) union cvmx_helper_link_info link_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int interface = cvmx_helper_get_interface_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int index = cvmx_helper_get_interface_index_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __cvmx_helper_sgmii_hardware_init_link(interface, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) link_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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