^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***********************license start***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Author: Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Contact: support@caviumnetworks.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the OCTEON SDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003-2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License, Version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NONINFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this file; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * or visit http://www.gnu.org/licenses/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file may also be available under a different license from Cavium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Contact Cavium Networks for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ***********************license end**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Helper functions to abstract board specific data about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * network ports from the rest of the cvmx-helper files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/octeon/cvmx-bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/octeon/cvmx-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/octeon/cvmx-helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/octeon/cvmx-helper-util.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/octeon/cvmx-helper-board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/octeon/cvmx-gmxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/octeon/cvmx-asxx-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Return the MII PHY address associated with the given IPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * port. A result of -1 means there isn't a MII capable PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * connected to this port. On chips supporting multiple MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * busses the bus number is encoded in bits <15:8>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * This function must be modified for every new Octeon board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Internally it uses switch statements based on the cvmx_sysinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * data to determine board types and revisions. It replies on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * fact that every Octeon board receives a unique board type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * enumeration from the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @ipd_port: Octeon IPD port to get the MII address for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Returns MII PHY address and bus number or -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int cvmx_helper_board_get_mii_address(int ipd_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) switch (cvmx_sysinfo_get()->board_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case CVMX_BOARD_TYPE_SIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Simulator doesn't have MII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case CVMX_BOARD_TYPE_EBT3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case CVMX_BOARD_TYPE_EBT5800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case CVMX_BOARD_TYPE_THUNDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case CVMX_BOARD_TYPE_NICPRO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Interface 0 is SPI4, interface 1 is RGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if ((ipd_port >= 16) && (ipd_port < 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ipd_port - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case CVMX_BOARD_TYPE_KODAMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case CVMX_BOARD_TYPE_EBH3100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case CVMX_BOARD_TYPE_HIKARI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Port 0 is WAN connected to a PHY, Port 1 is GMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * connected to a switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ipd_port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else if (ipd_port == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case CVMX_BOARD_TYPE_NAC38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Board has 8 RGMII ports PHYs are 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if ((ipd_port >= 0) && (ipd_port < 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ipd_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else if ((ipd_port >= 16) && (ipd_port < 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ipd_port - 16 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case CVMX_BOARD_TYPE_EBH3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Board has dual SPI4 and no PHYs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case CVMX_BOARD_TYPE_EBH5200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case CVMX_BOARD_TYPE_EBH5201:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case CVMX_BOARD_TYPE_EBT5200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Board has 2 management ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Board has 4 SGMII ports. The PHYs start right after the MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((ipd_port >= 0) && (ipd_port < 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ipd_port + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case CVMX_BOARD_TYPE_EBH5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case CVMX_BOARD_TYPE_EBH5601:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case CVMX_BOARD_TYPE_EBH5610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Board has 1 management port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Board has 8 SGMII ports. 4 connect out, two connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * to a switch, and 2 loop to each other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((ipd_port >= 0) && (ipd_port < 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ipd_port + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case CVMX_BOARD_TYPE_CUST_NB5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ipd_port == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case CVMX_BOARD_TYPE_NIC_XLE_4G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Board has 4 SGMII ports. connected QLM3(interface 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if ((ipd_port >= 16) && (ipd_port < 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ipd_port - 16 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case CVMX_BOARD_TYPE_NIC_XLE_10G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case CVMX_BOARD_TYPE_NIC10E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case CVMX_BOARD_TYPE_NIC4E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ipd_port >= 0 && ipd_port <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return (ipd_port + 0x1f) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case CVMX_BOARD_TYPE_NIC2E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ipd_port >= 0 && ipd_port <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ipd_port + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case CVMX_BOARD_TYPE_BBGW_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * No PHYs are connected to Octeon, everything is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * through switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case CVMX_BOARD_TYPE_CUST_WSX16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ipd_port >= 0 && ipd_port <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ipd_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else if (ipd_port >= 16 && ipd_port <= 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ipd_port - 16 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case CVMX_BOARD_TYPE_UBNT_E100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ipd_port >= 0 && ipd_port <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 7 - ipd_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case CVMX_BOARD_TYPE_KONTRON_S1901:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Some unknown board. Somebody forgot to update this function... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cvmx_dprintf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cvmx_sysinfo_get()->board_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * This function is the board specific method of determining an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * ethernet ports link speed. Most Octeon boards have Marvell PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * and are handled by the fall through case. This function must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * updated for boards that don't have the normal Marvell PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * This function must be modified for every new Octeon board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Internally it uses switch statements based on the cvmx_sysinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * data to determine board types and revisions. It relies on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * fact that every Octeon board receives a unique board type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * enumeration from the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @ipd_port: IPD input port associated with the port we want to get link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * status for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Returns The ports link status. If the link isn't fully resolved, this must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * return zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) union cvmx_helper_link_info result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) WARN(!octeon_is_simulation(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "Using deprecated link status - please update your DT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Unless we fix it later, all links are defaulted to down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (octeon_is_simulation()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* The simulator gives you a simulated 1Gbps full duplex link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) result.s.link_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) result.s.full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) result.s.speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) || OCTEON_IS_MODEL(OCTEON_CN58XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * We don't have a PHY address, so attempt to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * in-band status. It is really important that boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * not supporting in-band status never get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * here. Reading broken in-band status tends to do bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) union cvmx_gmxx_rxx_rx_inbnd inband_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int interface = cvmx_helper_get_interface_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int index = cvmx_helper_get_interface_index_num(ipd_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) inband_status.u64 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) result.s.link_up = inband_status.s.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) result.s.full_duplex = inband_status.s.duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) switch (inband_status.s.speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 0: /* 10 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) result.s.speed = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 1: /* 100 Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) result.s.speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case 2: /* 1 Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) result.s.speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 3: /* Illegal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * We don't have a PHY address and we don't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * in-band status. There is no way to determine the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * link speed. Return down assuming this port isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* If link is down, return all fields as zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!result.s.link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) result.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * This function is called by cvmx_helper_interface_probe() after it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * determines the number of ports Octeon can support on a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * interface. This function is the per board location to override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * this value. It is called with the number of ports Octeon might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * support and should return the number of actual ports on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * This function must be modifed for every new Octeon board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Internally it uses switch statements based on the cvmx_sysinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * data to determine board types and revisions. It relys on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * fact that every Octeon board receives a unique board type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * enumeration from the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @interface: Interface to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @supported_ports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Number of ports Octeon supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Returns Number of ports the actual board supports. Many times this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * simple be "support_ports".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (cvmx_sysinfo_get()->board_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (interface == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case CVMX_BOARD_TYPE_BBGW_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (interface == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case CVMX_BOARD_TYPE_NIC_XLE_4G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (interface == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) which we don't support. Disable ports connected to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case CVMX_BOARD_TYPE_EBH5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (interface == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return supported_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Get the clock type used for the USB block based on board type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Used by the USB code for auto configuration of clock type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Return USB clock type enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) switch (cvmx_sysinfo_get()->board_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case CVMX_BOARD_TYPE_BBGW_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case CVMX_BOARD_TYPE_LANAI2_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case CVMX_BOARD_TYPE_LANAI2_U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case CVMX_BOARD_TYPE_LANAI2_G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case CVMX_BOARD_TYPE_NIC10E_66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case CVMX_BOARD_TYPE_UBNT_E100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return USB_CLOCK_TYPE_CRYSTAL_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case CVMX_BOARD_TYPE_NIC10E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return USB_CLOCK_TYPE_REF_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Most boards except NIC10e use a 12MHz crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (OCTEON_IS_OCTEON2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return USB_CLOCK_TYPE_CRYSTAL_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return USB_CLOCK_TYPE_REF_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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