Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2000, 2001  Ralf Baechle <ralf@gnu.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * IP32 changes by Ilya.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2010 Cavium Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dma-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/swiotlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/octeon/pci-octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/octeon/cvmx-npi-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/octeon/cvmx-pci-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct octeon_dma_map_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		paddr -= 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return octeon_hole_phys_to_dma(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	daddr = octeon_hole_dma_to_phys(daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		daddr += 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static const struct octeon_dma_map_ops octeon_gen1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.phys_to_dma	= octeon_gen1_phys_to_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.dma_to_phys	= octeon_gen1_dma_to_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return octeon_hole_phys_to_dma(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return octeon_hole_dma_to_phys(daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const struct octeon_dma_map_ops octeon_gen2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.phys_to_dma	= octeon_gen2_phys_to_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.dma_to_phys	= octeon_gen2_dma_to_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		paddr -= 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Anything in the BAR1 hole or above goes via BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (paddr >= 0xf0000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		daddr += 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct octeon_dma_map_ops octeon_big_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.phys_to_dma	= octeon_big_phys_to_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.dma_to_phys	= octeon_big_dma_to_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 					   phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		paddr -= 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Anything not in the BAR1 range goes via BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		paddr = paddr - octeon_bar1_pci_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					    dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		daddr += octeon_bar1_pci_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		daddr += 0x400000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct octeon_dma_map_ops octeon_small_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.phys_to_dma	= octeon_small_phys_to_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.dma_to_phys	= octeon_small_dma_to_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void __init octeon_pci_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	switch (octeon_dma_bar_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case OCTEON_DMA_BAR_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		octeon_pci_dma_ops = &octeon_gen1_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	case OCTEON_DMA_BAR_TYPE_PCIE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		octeon_pci_dma_ops = &octeon_gen2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	case OCTEON_DMA_BAR_TYPE_BIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		octeon_pci_dma_ops = &octeon_big_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case OCTEON_DMA_BAR_TYPE_SMALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		octeon_pci_dma_ops = &octeon_small_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (dev && dev_is_pci(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (dev && dev_is_pci(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) char *octeon_swiotlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __init plat_swiotlb_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	phys_addr_t start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	phys_addr_t max_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	phys_addr_t addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	size_t swiotlbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned long swiotlb_nslabs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	max_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	addr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	for_each_mem_range(i, &start, &end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		/* These addresses map low for PCI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (start > 0x410000000ull && !OCTEON_IS_OCTEON2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		addr_size += (end - start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		if (max_addr < end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			max_addr = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	swiotlbsize = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * size to a maximum of 64MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (OCTEON_IS_MODEL(OCTEON_CN31XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	    || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		swiotlbsize = addr_size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (swiotlbsize > 64 * (1<<20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			swiotlbsize = 64 * (1<<20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	} else if (max_addr > 0xf0000000ul) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * Otherwise only allocate a big iotlb if there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 * memory past the BAR1 hole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		swiotlbsize = 64 * (1<<20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* OCTEON II ohci is only 32-bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		swiotlbsize = 64 * (1<<20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (!octeon_swiotlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		panic("%s: Failed to allocate %zu bytes align=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		      __func__, swiotlbsize, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		panic("Cannot allocate SWIOTLB buffer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }