^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 by Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009, 2012 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/octeon/cvmx-ipd-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/octeon/cvmx-mio-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/octeon/cvmx-rst-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/octeon/cvmx-fpa-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u64 f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u64 rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static u64 sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u64 octeon_udelay_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static u64 octeon_ndelay_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __init octeon_setup_delays(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * For __ndelay we divide by 2^16, so the factor is multiplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * by the same amount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) preset_lpj = octeon_get_clock_rate() / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) union cvmx_mio_rst_boot rst_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) rdiv = rst_boot.s.c_mul; /* CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sdiv = rst_boot.s.pnr_mul; /* I/O clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) f = (0x8000000000000000ull / sdiv) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } else if (current_cpu_type() == CPU_CAVIUM_OCTEON3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) union cvmx_rst_boot rst_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) rdiv = rst_boot.s.c_mul; /* CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sdiv = rst_boot.s.pnr_mul; /* I/O clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) f = (0x8000000000000000ull / sdiv) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Set the current core's cvmcount counter to the value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * IPD_CLK_COUNT. We do this on all cores as they are brought
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * on-line. This allows for a read from a local cpu register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * access a synchronized counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void octeon_init_cvmcount(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u64 clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned loops = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_reg = octeon_has_feature(OCTEON_FEATURE_FPA3) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CVMX_FPA_CLK_COUNT : CVMX_IPD_CLK_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Clobber loops so GCC will not unroll the following while loop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) asm("" : "+r" (loops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Loop several times so we are executing from the cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * which should give more deterministic timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) while (loops--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u64 clk_count = cvmx_read_csr(clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (rdiv != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_count *= rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (f != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) asm("dmultu\t%[cnt],%[f]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "mfhi\t%[cnt]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) : [cnt] "+r" (clk_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) : [f] "r" (f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) : "hi", "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) write_c0_cvmcount(clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static u64 octeon_cvmcount_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct clocksource clocksource_mips = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "OCTEON_CVMCOUNT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .read = octeon_cvmcount_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long long notrace sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 64-bit arithmatic can overflow, so use 128-bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 t1, t2, t3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long long rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u64 mult = clocksource_mips.mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u64 shift = clocksource_mips.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 cnt = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) asm (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "dmultu\t%[cnt],%[mult]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "nor\t%[t1],$0,%[shift]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "mfhi\t%[t2]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "mflo\t%[t3]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "dsll\t%[t2],%[t2],1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "dsrlv\t%[rv],%[t3],%[shift]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "dsllv\t%[t1],%[t2],%[t1]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "or\t%[rv],%[t1],%[rv]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) : "hi", "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clocksource_mips.rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __udelay(unsigned long us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 cur, end, inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) inc = us * octeon_udelay_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) end = cur + inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) while (end > cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EXPORT_SYMBOL(__udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __ndelay(unsigned long ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u64 cur, end, inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) inc = ((ns * octeon_ndelay_factor) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) end = cur + inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (end > cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EXPORT_SYMBOL(__ndelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __delay(unsigned long loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 cur, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) end = cur + loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while (end > cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) EXPORT_SYMBOL(__delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * octeon_io_clk_delay - wait for a given number of io clock cycles to pass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * We scale the wait by the clock ratio, and then wait for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * corresponding number of core clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @count: The number of clocks to wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void octeon_io_clk_delay(unsigned long count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 cur, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (rdiv != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) end = count * rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (f != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) asm("dmultu\t%[cnt],%[f]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "mfhi\t%[cnt]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) : [cnt] "+r" (end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) : [f] "r" (f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) : "hi", "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) end = cur + end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) end = cur + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) while (end > cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cur = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL(octeon_io_clk_delay);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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