^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) if CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) config CAVIUM_CN63XXP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) bool "Enable CN63XXP1 errata workarounds"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) default "n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) The CN63XXP1 chip requires build time workarounds to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) function reliably, select this option to enable them. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) workarounds will cause a slight decrease in performance on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) non-CN63XXP1 hardware, so it is recommended to select "n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) unless it is known the workarounds are needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) config CAVIUM_OCTEON_CVMSEG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int "Number of L1 cache lines reserved for CVMSEG memory"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) range 0 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) default 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CVMSEG LM is a segment that accesses portions of the dcache as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) local memory; the larger CVMSEG is, the smaller the cache is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) This selects the size of CVMSEG LM, which is in cache blocks. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) between zero and 6192 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) endif # CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if CAVIUM_OCTEON_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) config CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool "Lock often used kernel code in the L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Enable locking parts of the kernel into the L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) config CAVIUM_OCTEON_LOCK_L2_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool "Lock the TLB handler in L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) depends on CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Lock the low level TLB fast path into L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool "Lock the exception handler in L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) depends on CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Lock the low level exception handler into L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bool "Lock the interrupt handler in L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) depends on CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Lock the low level interrupt handler into L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool "Lock the 2nd level interrupt handler in L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) depends on CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Lock the 2nd level interrupt handler in L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) config CAVIUM_OCTEON_LOCK_L2_MEMCPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool "Lock memcpy() in L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) depends on CAVIUM_OCTEON_LOCK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) default "y"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Lock the kernel's implementation of memcpy() into L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) config OCTEON_ILM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tristate "Module to measure interrupt latency using Octeon CIU Timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) This driver is a module to measure interrupt latency using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) the CIU Timers on Octeon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) To compile this driver as a module, choose M here. The module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) will be called octeon-ilm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) endif # CAVIUM_OCTEON_SOC
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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