Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * 16550 compatible uart based serial debug support for zboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #if defined(CONFIG_MACH_LOONGSON64) || defined(CONFIG_MIPS_MALTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UART_BASE 0x1fd003f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifdef CONFIG_AR7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <ar7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_MACH_INGENIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define INGENIC_UART0_BASE_ADDR	0x10030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_CPU_XLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UART0_BASE  0x1EF14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IOTYPE unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_CPU_XLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UART0_BASE  0x18030100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IOTYPE unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef IOTYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IOTYPE char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #error please define the serial port address for your own machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline unsigned int serial_in(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	return *((volatile IOTYPE *)PORT(offset)) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void serial_out(int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	*((volatile IOTYPE *)PORT(offset)) = value & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void putc(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	int timeout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	serial_out(UART_TX, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }