Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/bmips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/smp-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RELO_NORMAL_VEC		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_BCM6328_OTP		((void __iomem *)CKSEG1ADDR(0x1000062c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define BCM6328_TP1_DISABLED	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct bmips_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	const char		*compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	void			(*quirk_fn)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void kbase_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	__raw_writel(kbase | RELO_NORMAL_VEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		     BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ebase = kbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void bcm3384_viper_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * Some experimental CM boxes are set up to let CM own the Viper TP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * and let Linux own TP1.  This requires moving the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * load address to a non-conflicting region (e.g. via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * If we detect this condition, we need to move the MIPS exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * vectors up to an area that we own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * This is distinct from the OTHER special case mentioned in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * logical CPU#1).  For the Viper TP1 case, SMP is off limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * Also note that many BMIPS435x CPUs do not have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	board_ebase_setup = &kbase_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bmips_smp_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void bcm63xx_fixup_cpu1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * The bootloader has set up the CPU1 reset vector at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * 0xa000_0200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * This conflicts with the special interrupt vector (IV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * The bootloader has also set up CPU1 to respond to the wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * IPI interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * Here we will start up CPU1 in the background and ask it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * reconfigure itself then go back to sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	__sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	set_c0_cause(C_SW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	cpumask_set_cpu(1, &bmips_booted_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void bcm6328_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Check CPU1 status in OTP (it is usually disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		bmips_smp_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		bcm63xx_fixup_cpu1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static void bcm6358_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * BCM3368/BCM6358 need special handling for their shared TLB, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * disable SMP for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	bmips_smp_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void bcm6368_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	bcm63xx_fixup_cpu1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct bmips_quirk bmips_quirk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ "brcm,bcm3368",		&bcm6358_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{ "brcm,bcm3384-viper",		&bcm3384_viper_quirks		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{ "brcm,bcm33843-viper",	&bcm3384_viper_quirks		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ "brcm,bcm6328",		&bcm6328_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ "brcm,bcm6358",		&bcm6358_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ "brcm,bcm6362",		&bcm6368_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ "brcm,bcm6368",		&bcm6368_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ "brcm,bcm63168",		&bcm6368_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ "brcm,bcm63268",		&bcm6368_quirks			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __init prom_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	bmips_cpu_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	register_bmips_smp_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __init prom_free_prom_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return "Generic BMIPS kernel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	np = of_find_node_by_name(NULL, "cpus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		panic("missing 'cpus' DT node");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		panic("missing 'mips-hpt-frequency' property");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	mips_hpt_frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	void *dtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	const struct bmips_quirk *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	set_io_port_base(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ioport_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ioport_resource.end = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		dtb = phys_to_virt(fw_arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	else if (fw_passed_dtb) /* UHI interface or appended dtb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		dtb = (void *)fw_passed_dtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	else if (__dtb_start != __dtb_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dtb = (void *)__dtb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		panic("no dtb found");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	__dt_setup_arch(dtb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	for (q = bmips_quirk_list; q->quirk_fn; q++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					     q->compatible)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			q->quirk_fn();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __init device_tree_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	np = of_find_node_by_name(NULL, "cpus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (np && of_get_available_child_count(np) <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		bmips_smp_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int __init plat_dev_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) device_initcall(plat_dev_init);