Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <bcm63xx_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <bcm63xx_io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <bcm63xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <bcm63xx_reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define __GEN_RESET_BITS_TABLE(__cpu)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	[BCM63XX_RESET_SPI]		= BCM## __cpu ##_RESET_SPI,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	[BCM63XX_RESET_ENET]		= BCM## __cpu ##_RESET_ENET,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	[BCM63XX_RESET_USBH]		= BCM## __cpu ##_RESET_USBH,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	[BCM63XX_RESET_USBD]		= BCM## __cpu ##_RESET_USBD,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	[BCM63XX_RESET_DSL]		= BCM## __cpu ##_RESET_DSL,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	[BCM63XX_RESET_SAR]		= BCM## __cpu ##_RESET_SAR,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	[BCM63XX_RESET_EPHY]		= BCM## __cpu ##_RESET_EPHY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	[BCM63XX_RESET_ENETSW]		= BCM## __cpu ##_RESET_ENETSW,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	[BCM63XX_RESET_PCM]		= BCM## __cpu ##_RESET_PCM,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	[BCM63XX_RESET_MPI]		= BCM## __cpu ##_RESET_MPI,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	[BCM63XX_RESET_PCIE]		= BCM## __cpu ##_RESET_PCIE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	[BCM63XX_RESET_PCIE_EXT]	= BCM## __cpu ##_RESET_PCIE_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BCM3368_RESET_SPI	SOFTRESET_3368_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define BCM3368_RESET_ENET	SOFTRESET_3368_ENET_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BCM3368_RESET_USBH	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define BCM3368_RESET_USBD	SOFTRESET_3368_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BCM3368_RESET_DSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define BCM3368_RESET_SAR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define BCM3368_RESET_EPHY	SOFTRESET_3368_EPHY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BCM3368_RESET_ENETSW	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BCM3368_RESET_PCM	SOFTRESET_3368_PCM_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BCM3368_RESET_MPI	SOFTRESET_3368_MPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BCM3368_RESET_PCIE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BCM3368_RESET_PCIE_EXT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BCM6328_RESET_SPI	SOFTRESET_6328_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BCM6328_RESET_ENET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BCM6328_RESET_USBH	SOFTRESET_6328_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BCM6328_RESET_USBD	SOFTRESET_6328_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BCM6328_RESET_DSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BCM6328_RESET_SAR	SOFTRESET_6328_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BCM6328_RESET_EPHY	SOFTRESET_6328_EPHY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BCM6328_RESET_ENETSW	SOFTRESET_6328_ENETSW_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BCM6328_RESET_PCM	SOFTRESET_6328_PCM_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BCM6328_RESET_MPI	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BCM6328_RESET_PCIE	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				(SOFTRESET_6328_PCIE_MASK |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				 SOFTRESET_6328_PCIE_CORE_MASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				 SOFTRESET_6328_PCIE_HARD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BCM6328_RESET_PCIE_EXT	SOFTRESET_6328_PCIE_EXT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define BCM6338_RESET_SPI	SOFTRESET_6338_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define BCM6338_RESET_ENET	SOFTRESET_6338_ENET_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define BCM6338_RESET_USBH	SOFTRESET_6338_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define BCM6338_RESET_USBD	SOFTRESET_6338_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define BCM6338_RESET_DSL	SOFTRESET_6338_ADSL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BCM6338_RESET_SAR	SOFTRESET_6338_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BCM6338_RESET_EPHY	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BCM6338_RESET_ENETSW	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define BCM6338_RESET_PCM	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define BCM6338_RESET_MPI	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define BCM6338_RESET_PCIE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define BCM6338_RESET_PCIE_EXT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define BCM6348_RESET_SPI	SOFTRESET_6348_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define BCM6348_RESET_ENET	SOFTRESET_6348_ENET_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define BCM6348_RESET_USBH	SOFTRESET_6348_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define BCM6348_RESET_USBD	SOFTRESET_6348_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define BCM6348_RESET_DSL	SOFTRESET_6348_ADSL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define BCM6348_RESET_SAR	SOFTRESET_6348_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define BCM6348_RESET_EPHY	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define BCM6348_RESET_ENETSW	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define BCM6348_RESET_PCM	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define BCM6348_RESET_MPI	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define BCM6348_RESET_PCIE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define BCM6348_RESET_PCIE_EXT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define BCM6358_RESET_SPI	SOFTRESET_6358_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define BCM6358_RESET_ENET	SOFTRESET_6358_ENET_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define BCM6358_RESET_USBH	SOFTRESET_6358_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define BCM6358_RESET_USBD	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define BCM6358_RESET_DSL	SOFTRESET_6358_ADSL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define BCM6358_RESET_SAR	SOFTRESET_6358_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define BCM6358_RESET_EPHY	SOFTRESET_6358_EPHY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define BCM6358_RESET_ENETSW	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define BCM6358_RESET_PCM	SOFTRESET_6358_PCM_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define BCM6358_RESET_MPI	SOFTRESET_6358_MPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define BCM6358_RESET_PCIE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BCM6358_RESET_PCIE_EXT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BCM6362_RESET_SPI	SOFTRESET_6362_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BCM6362_RESET_ENET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BCM6362_RESET_USBH	SOFTRESET_6362_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCM6362_RESET_USBD	SOFTRESET_6362_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BCM6362_RESET_DSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BCM6362_RESET_SAR	SOFTRESET_6362_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BCM6362_RESET_EPHY	SOFTRESET_6362_EPHY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM6362_RESET_ENETSW	SOFTRESET_6362_ENETSW_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BCM6362_RESET_PCM	SOFTRESET_6362_PCM_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BCM6362_RESET_MPI	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				 SOFTRESET_6362_PCIE_CORE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BCM6362_RESET_PCIE_EXT	SOFTRESET_6362_PCIE_EXT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BCM6368_RESET_SPI	SOFTRESET_6368_SPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BCM6368_RESET_ENET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BCM6368_RESET_USBH	SOFTRESET_6368_USBH_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BCM6368_RESET_USBD	SOFTRESET_6368_USBS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BCM6368_RESET_DSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BCM6368_RESET_SAR	SOFTRESET_6368_SAR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BCM6368_RESET_EPHY	SOFTRESET_6368_EPHY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BCM6368_RESET_ENETSW	SOFTRESET_6368_ENETSW_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BCM6368_RESET_PCM	SOFTRESET_6368_PCM_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BCM6368_RESET_MPI	SOFTRESET_6368_MPI_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BCM6368_RESET_PCIE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BCM6368_RESET_PCIE_EXT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * core reset bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const u32 bcm3368_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	__GEN_RESET_BITS_TABLE(3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const u32 bcm6328_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	__GEN_RESET_BITS_TABLE(6328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const u32 bcm6338_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	__GEN_RESET_BITS_TABLE(6338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const u32 bcm6348_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__GEN_RESET_BITS_TABLE(6348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const u32 bcm6358_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	__GEN_RESET_BITS_TABLE(6358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const u32 bcm6362_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	__GEN_RESET_BITS_TABLE(6362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const u32 bcm6368_reset_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__GEN_RESET_BITS_TABLE(6368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const u32 *bcm63xx_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int reset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int __init bcm63xx_reset_bits_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (BCMCPU_IS_3368()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		reset_reg = PERF_SOFTRESET_6358_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		bcm63xx_reset_bits = bcm3368_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} else if (BCMCPU_IS_6328()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		reset_reg = PERF_SOFTRESET_6328_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		bcm63xx_reset_bits = bcm6328_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	} else if (BCMCPU_IS_6338()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		reset_reg = PERF_SOFTRESET_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		bcm63xx_reset_bits = bcm6338_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	} else if (BCMCPU_IS_6348()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		reset_reg = PERF_SOFTRESET_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		bcm63xx_reset_bits = bcm6348_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	} else if (BCMCPU_IS_6358()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		reset_reg = PERF_SOFTRESET_6358_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		bcm63xx_reset_bits = bcm6358_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	} else if (BCMCPU_IS_6362()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		reset_reg = PERF_SOFTRESET_6362_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		bcm63xx_reset_bits = bcm6362_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	} else if (BCMCPU_IS_6368()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		reset_reg = PERF_SOFTRESET_6368_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		bcm63xx_reset_bits = bcm6368_reset_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static DEFINE_SPINLOCK(reset_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void __bcm63xx_core_set_reset(u32 mask, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	spin_lock_irqsave(&reset_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	val = bcm_perf_readl(reset_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	bcm_perf_writel(val, reset_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	spin_unlock_irqrestore(&reset_mutex, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void bcm63xx_core_set_reset(enum bcm63xx_core_reset core, int reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	__bcm63xx_core_set_reset(bcm63xx_reset_bits[core], reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) EXPORT_SYMBOL(bcm63xx_core_set_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) postcore_initcall(bcm63xx_reset_bits_init);