^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <bcm63xx_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <bcm63xx_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <bcm63xx_io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <bcm63xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u32 gpio_out_low_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void bcm63xx_gpio_out_low_reg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) switch (bcm63xx_get_cpu_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) case BCM6345_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) gpio_out_low_reg = GPIO_DATA_LO_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static u32 gpio_out_low, gpio_out_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void bcm63xx_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 *v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (gpio >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (gpio < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = gpio_out_low_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mask = 1 << gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) v = &gpio_out_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reg = GPIO_DATA_HI_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mask = 1 << (gpio - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) v = &gpio_out_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *v |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bcm_gpio_writel(*v, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (gpio >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (gpio < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = gpio_out_low_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mask = 1 << gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = GPIO_DATA_HI_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mask = 1 << (gpio - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return !!(bcm_gpio_readl(reg) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned gpio, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (gpio >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (gpio < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg = GPIO_CTL_LO_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mask = 1 << gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = GPIO_CTL_HI_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mask = 1 << (gpio - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tmp = bcm_gpio_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (dir == BCM63XX_GPIO_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bcm_gpio_writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bcm63xx_gpio_set(chip, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct gpio_chip bcm63xx_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .label = "bcm63xx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .direction_input = bcm63xx_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .direction_output = bcm63xx_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .get = bcm63xx_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .set = bcm63xx_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int __init bcm63xx_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bcm63xx_gpio_out_low_reg_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!BCMCPU_IS_6345())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return gpiochip_add_data(&bcm63xx_gpio_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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