Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <bcm63xx_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <bcm63xx_io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <bcm63xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <bcm63xx_reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	void		(*set)(struct clk *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int	rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned int	usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	int		id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static DEFINE_MUTEX(clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static void clk_enable_unlocked(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (clk->set && (clk->usage++) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		clk->set(clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void clk_disable_unlocked(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (clk->set && (--clk->usage) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		clk->set(clk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static void bcm_hwclock_set(u32 mask, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	reg = bcm_perf_readl(PERF_CKCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		reg |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	bcm_perf_writel(reg, PERF_CKCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void enet_misc_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (BCMCPU_IS_6338())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		mask = CKCTL_6338_ENET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	else if (BCMCPU_IS_6345())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		mask = CKCTL_6345_ENET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	else if (BCMCPU_IS_6348())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		mask = CKCTL_6348_ENET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		/* BCMCPU_IS_6358 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		mask = CKCTL_6358_EMUSB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bcm_hwclock_set(mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static struct clk clk_enet_misc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.set	= enet_misc_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * Ethernet MAC clocks: only revelant on 6358, silently enable misc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static void enetx_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		clk_enable_unlocked(&clk_enet_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		clk_disable_unlocked(&clk_enet_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (clk->id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			mask = CKCTL_6358_ENET0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			mask = CKCTL_6358_ENET1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		bcm_hwclock_set(mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk clk_enet0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.id	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.set	= enetx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk clk_enet1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.id	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set	= enetx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * Ethernet PHY clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void ephy_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clk clk_ephy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.set	= ephy_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * Ethernet switch SAR clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void swpkt_sar_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct clk clk_swpkt_sar = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.set	= swpkt_sar_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * Ethernet switch USB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void swpkt_usb_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct clk clk_swpkt_usb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.set	= swpkt_usb_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * Ethernet switch clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void enetsw_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (BCMCPU_IS_6328()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	} else if (BCMCPU_IS_6362()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	} else if (BCMCPU_IS_6368()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			clk_enable_unlocked(&clk_swpkt_sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			clk_enable_unlocked(&clk_swpkt_usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			clk_disable_unlocked(&clk_swpkt_usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			clk_disable_unlocked(&clk_swpkt_sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/* reset switch core afer clock change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct clk clk_enetsw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.set	= enetsw_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * PCM clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void pcm_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (BCMCPU_IS_3368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (BCMCPU_IS_6358())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct clk clk_pcm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.set	= pcm_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * USB host clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void usbh_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (BCMCPU_IS_6328())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	else if (BCMCPU_IS_6348())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else if (BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct clk clk_usbh = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.set	= usbh_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * USB device clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void usbd_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (BCMCPU_IS_6328())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	else if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	else if (BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct clk clk_usbd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.set	= usbd_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * SPI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void spi_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (BCMCPU_IS_6338())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		mask = CKCTL_6338_SPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	else if (BCMCPU_IS_6348())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		mask = CKCTL_6348_SPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		mask = CKCTL_6358_SPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	else if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		mask = CKCTL_6362_SPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		/* BCMCPU_IS_6368 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		mask = CKCTL_6368_SPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	bcm_hwclock_set(mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct clk clk_spi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.set	= spi_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * HSSPI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void hsspi_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (BCMCPU_IS_6328())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		mask = CKCTL_6328_HSSPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	else if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		mask = CKCTL_6362_HSSPI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	bcm_hwclock_set(mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct clk clk_hsspi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.set	= hsspi_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * HSSPI PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct clk clk_hsspi_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * XTM clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void xtm_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		clk_enable_unlocked(&clk_swpkt_sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		clk_disable_unlocked(&clk_swpkt_sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		/* reset sar core afer clock change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct clk clk_xtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.set	= xtm_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * IPsec clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void ipsec_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	else if (BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct clk clk_ipsec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.set	= ipsec_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * PCIe clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void pcie_set(struct clk *clk, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (BCMCPU_IS_6328())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	else if (BCMCPU_IS_6362())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct clk clk_pcie = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.set	= pcie_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)  * Internal peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct clk clk_periph = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.rate	= (50 * 1000 * 1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * Linux clock API implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int clk_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	clk_enable_unlocked(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) EXPORT_SYMBOL(clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void clk_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	clk_disable_unlocked(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) EXPORT_SYMBOL(clk_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct clk *clk_get_parent(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) EXPORT_SYMBOL(clk_get_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int clk_set_parent(struct clk *clk, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) EXPORT_SYMBOL(clk_set_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long clk_get_rate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) EXPORT_SYMBOL(clk_get_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int clk_set_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) EXPORT_SYMBOL_GPL(clk_set_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) long clk_round_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) EXPORT_SYMBOL_GPL(clk_round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct clk_lookup bcm3368_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct clk_lookup bcm6328_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct clk_lookup bcm6338_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct clk_lookup bcm6345_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct clk_lookup bcm6348_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct clk_lookup bcm6358_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static struct clk_lookup bcm6362_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct clk_lookup bcm6368_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	/* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	CLKDEV_INIT(NULL, "periph", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	/* gated clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	CLKDEV_INIT(NULL, "spi", &clk_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	CLKDEV_INIT(NULL, "xtm", &clk_xtm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define HSSPI_PLL_HZ_6328	133333333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define HSSPI_PLL_HZ_6362	400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int __init bcm63xx_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	switch (bcm63xx_get_cpu_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	case BCM3368_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	case BCM6328_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	case BCM6338_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	case BCM6345_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	case BCM6348_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	case BCM6358_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	case BCM6362_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	case BCM6368_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) arch_initcall(bcm63xx_clk_init);