^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <bcm47xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <bcm47xx_board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 chip_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) char buf[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum bcm47xx_board board = bcm47xx_board_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Use deterministic values for initial counter interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * so that calibrate delay avoids encountering a counter wrap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) write_c0_count(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) write_c0_compare(0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) chip_id = bcm47xx_bus.ssb.chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (chip_id == 0x5354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (len >= 0 && !strncmp(buf, "200", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hz = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) switch (board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case BCM47XX_BOARD_ASUS_WL520GC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case BCM47XX_BOARD_ASUS_WL520GU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) hz = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hz = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mips_hpt_frequency = hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }