Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2006 Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2010 Waldemar Brodkorb <wbx@openadk.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  This program is free software; you can redistribute  it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  under  the terms of  the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Free Software Foundation;  either version 2 of the  License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "bcm47xx_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/bcm47xx_sprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/phy_fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/ssb/ssb_embedded.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/bcma/bcma_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <bcm47xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <bcm47xx_board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) union bcm47xx_bus bcm47xx_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) EXPORT_SYMBOL(bcm47xx_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) enum bcm47xx_bus_type bcm47xx_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) EXPORT_SYMBOL(bcm47xx_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static void bcm47xx_machine_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pr_alert("Please stand by while rebooting the system...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* Set the watchdog timer to reset immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		if (bcm47xx_bus.ssb.chip_id == 0x4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			write_c0_diag4(1 << 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		if (bcm47xx_bus.ssb.chip_id == 0x4785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			__asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 				".set\tmips3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				"sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 				"wait\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				".set\tmips0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void bcm47xx_machine_halt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Disable interrupts and watchdog and spin forever */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __init bcm47xx_register_ssb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	char buf[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct ssb_mipscore *mcore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	err = ssb_bus_host_soc_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		panic("Failed to initialize SSB bus (err %d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mcore = &bcm47xx_bus.ssb.mipscore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (strstr(buf, "console=ttyS1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			struct ssb_serial_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			pr_debug("Swapping serial ports!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			/* swap serial ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			memcpy(&port, &mcore->serial_ports[0], sizeof(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			       sizeof(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			memcpy(&mcore->serial_ports[1], &port, sizeof(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void __init bcm47xx_register_bcma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	err = bcma_host_soc_register(&bcm47xx_bus.bcma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		panic("Failed to register BCMA bus (err %d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * Memory setup is done in the early part of MIPS's arch_mem_init. It's supposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * to detect memory and record it with memblock_add.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * Any extra initializaion performed here must not use kmalloc or bootmem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct cpuinfo_mips *c = &current_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (c->cputype == CPU_74K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pr_info("Using bcma bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		bcm47xx_register_bcma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		bcm47xx_prom_highmem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		pr_info("Using ssb bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		bcm47xx_sprom_register_fallbacks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		bcm47xx_register_ssb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	_machine_restart = bcm47xx_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	_machine_halt = bcm47xx_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pm_power_off = bcm47xx_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct device * __init bcm47xx_setup_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	err = dev_set_name(dev, "bcm47xx_soc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		pr_err("Failed to set SoC device name: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		pr_err("Failed to set SoC DMA mask: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * This finishes bus initialization doing things that were not possible without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * kmalloc. Make sure to call it late enough (after mm_init).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __init bcm47xx_bus_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (!bcm47xx_bus.bcma.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			panic("Failed to setup SoC device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		err = bcma_host_soc_init(&bcm47xx_bus.bcma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			panic("Failed to initialize BCMA bus (err %d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* With bus initialized we can access NVRAM and detect the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	bcm47xx_board_detect();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mips_set_machine_name(bcm47xx_board_get_name());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int __init bcm47xx_cpu_fixes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		/* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/* The BCM4706 has a problem with the CPU wait instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		 * When r4k_wait or r4k_wait_irqoff is used will just hang and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 * not return from a msleep(). Removing the cpu_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 * functionality is a workaround for this problem. The BCM4716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		 * does not have this problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			cpu_wait = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) arch_initcall(bcm47xx_cpu_fixes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.link	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.speed	= SPEED_100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.duplex	= DUPLEX_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int __init bcm47xx_register_bus_complete(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		/* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		if (device_register(bcm47xx_bus.bcma.dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			pr_err("Failed to register SoC device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		bcma_bus_register(&bcm47xx_bus.bcma.bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bcm47xx_buttons_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	bcm47xx_leds_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	bcm47xx_workarounds();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) device_initcall(bcm47xx_register_bus_complete);