Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * 8250 UART probe driver for the BCM47XX platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Author: Aurelien Jarno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <bcm47xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct plat_serial8250_port uart8250_data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct platform_device uart8250_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.platform_data	= uart8250_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int __init uart8250_init_ssb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct ssb_mipscore *mcore = &(bcm47xx_bus.ssb.mipscore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	memset(&uart8250_data, 0,  sizeof(uart8250_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	for (i = 0; i < mcore->nr_serial_ports &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		    i < ARRAY_SIZE(uart8250_data) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		struct plat_serial8250_port *p = &(uart8250_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		p->mapbase = (unsigned int)ssb_port->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		p->membase = (void *)ssb_port->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		p->irq = ssb_port->irq + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		p->uartclk = ssb_port->baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		p->regshift = ssb_port->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		p->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return platform_device_register(&uart8250_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int __init uart8250_init_bcma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct bcma_drv_cc *cc = &(bcm47xx_bus.bcma.bus.drv_cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	memset(&uart8250_data, 0,  sizeof(uart8250_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	for (i = 0; i < cc->nr_serial_ports &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		    i < ARRAY_SIZE(uart8250_data) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		struct plat_serial8250_port *p = &(uart8250_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		struct bcma_serial_port *bcma_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		bcma_port = &(cc->serial_ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		p->mapbase = (unsigned int)bcma_port->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		p->membase = (void *)bcma_port->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		p->irq = bcma_port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		p->uartclk = bcma_port->baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		p->regshift = bcma_port->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		p->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	return platform_device_register(&uart8250_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int __init uart8250_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	switch (bcm47xx_bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_BCM47XX_SSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	case BCM47XX_BUS_TYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		return uart8250_init_ssb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_BCM47XX_BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	case BCM47XX_BUS_TYPE_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 		return uart8250_init_bcma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) device_initcall(uart8250_init);