^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR71XX/AR724X/AR913X specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/time.h> /* for mips_hpt_frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/reboot.h> /* for _machine_{restart,halt} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/fw/fw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATH79_SYS_TYPE_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void ath79_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (cpu_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) cpu_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void ath79_halt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cpu_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __init ath79_detect_sys_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) char *chip = "????";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 ver = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) major = id & REV_ID_MAJOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) switch (major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case REV_ID_MAJOR_AR71XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) minor = id & AR71XX_REV_ID_MINOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rev &= AR71XX_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case AR71XX_REV_ID_MINOR_AR7130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ath79_soc = ATH79_SOC_AR7130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) chip = "7130";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case AR71XX_REV_ID_MINOR_AR7141:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ath79_soc = ATH79_SOC_AR7141;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) chip = "7141";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case AR71XX_REV_ID_MINOR_AR7161:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ath79_soc = ATH79_SOC_AR7161;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) chip = "7161";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case REV_ID_MAJOR_AR7240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ath79_soc = ATH79_SOC_AR7240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) chip = "7240";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rev = id & AR724X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case REV_ID_MAJOR_AR7241:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ath79_soc = ATH79_SOC_AR7241;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) chip = "7241";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rev = id & AR724X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case REV_ID_MAJOR_AR7242:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ath79_soc = ATH79_SOC_AR7242;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) chip = "7242";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rev = id & AR724X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case REV_ID_MAJOR_AR913X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) minor = id & AR913X_REV_ID_MINOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rev = id >> AR913X_REV_ID_REVISION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rev &= AR913X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) switch (minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case AR913X_REV_ID_MINOR_AR9130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ath79_soc = ATH79_SOC_AR9130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) chip = "9130";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case AR913X_REV_ID_MINOR_AR9132:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ath79_soc = ATH79_SOC_AR9132;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) chip = "9132";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case REV_ID_MAJOR_AR9330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ath79_soc = ATH79_SOC_AR9330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) chip = "9330";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rev = id & AR933X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case REV_ID_MAJOR_AR9331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ath79_soc = ATH79_SOC_AR9331;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chip = "9331";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rev = id & AR933X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case REV_ID_MAJOR_AR9341:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ath79_soc = ATH79_SOC_AR9341;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) chip = "9341";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rev = id & AR934X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case REV_ID_MAJOR_AR9342:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ath79_soc = ATH79_SOC_AR9342;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) chip = "9342";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rev = id & AR934X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case REV_ID_MAJOR_AR9344:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ath79_soc = ATH79_SOC_AR9344;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) chip = "9344";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rev = id & AR934X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case REV_ID_MAJOR_QCA9533_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ver = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ath79_soc_rev = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case REV_ID_MAJOR_QCA9533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ath79_soc = ATH79_SOC_QCA9533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) chip = "9533";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rev = id & QCA953X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case REV_ID_MAJOR_QCA9556:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ath79_soc = ATH79_SOC_QCA9556;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) chip = "9556";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rev = id & QCA955X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case REV_ID_MAJOR_QCA9558:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ath79_soc = ATH79_SOC_QCA9558;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip = "9558";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rev = id & QCA955X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case REV_ID_MAJOR_QCA956X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ath79_soc = ATH79_SOC_QCA956X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) chip = "956X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rev = id & QCA956X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case REV_ID_MAJOR_TP9343:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ath79_soc = ATH79_SOC_TP9343;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) chip = "9343";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rev = id & QCA956X_REV_ID_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) panic("ath79: unknown SoC, id:0x%08x", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ver == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ath79_soc_rev = rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chip, ver, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else if (soc_is_tp9343())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) chip, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_info("SoC: %s\n", ath79_sys_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ath79_sys_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int get_c0_compare_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return CP0_LEGACY_COMPARE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long fdt_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) set_io_port_base(KSEG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Get the position of the FDT passed by the bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) fdt_start = fw_getenvl("fdt_start");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (fdt_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __dt_setup_arch((void *)KSEG0ADDR(fdt_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else if (fw_passed_dtb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ath79_reset_base = ioremap(AR71XX_RESET_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) AR71XX_RESET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ath79_pll_base = ioremap(AR71XX_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) AR71XX_PLL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ath79_detect_sys_type();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ath79_ddr_ctrl_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) _machine_restart = ath79_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) _machine_halt = ath79_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pm_power_off = ath79_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long cpu_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) np = of_get_cpu_node(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pr_err("Failed to get CPU node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cpu_clk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_info("CPU clock: %lu.%03lu MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mips_hpt_frequency = cpu_clk_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __init device_tree_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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