^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR7XXX/AR9XXX SoC early printk support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ath79/ar933x_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void (*_prom_putchar)(char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) t = __raw_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if ((t & mask) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void prom_putchar_ar71xx(char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __raw_writel((unsigned char)ch, base + UART_TX * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void prom_putchar_ar933x(char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) AR933X_UART_DATA_TX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) base + AR933X_UART_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) AR933X_UART_DATA_TX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void prom_putchar_dummy(char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void prom_enable_uart(u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 uart_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case REV_ID_MAJOR_AR71XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uart_en = AR71XX_GPIO_FUNC_UART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case REV_ID_MAJOR_AR7240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case REV_ID_MAJOR_AR7241:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case REV_ID_MAJOR_AR7242:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uart_en = AR724X_GPIO_FUNC_UART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case REV_ID_MAJOR_AR913X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uart_en = AR913X_GPIO_FUNC_UART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case REV_ID_MAJOR_AR9330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case REV_ID_MAJOR_AR9331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uart_en = AR933X_GPIO_FUNC_UART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case REV_ID_MAJOR_AR9341:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case REV_ID_MAJOR_AR9342:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case REV_ID_MAJOR_AR9344:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) t |= uart_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void prom_putchar_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) id &= REV_ID_MAJOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case REV_ID_MAJOR_AR71XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case REV_ID_MAJOR_AR7240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case REV_ID_MAJOR_AR7241:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case REV_ID_MAJOR_AR7242:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case REV_ID_MAJOR_AR913X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case REV_ID_MAJOR_AR9341:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case REV_ID_MAJOR_AR9342:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case REV_ID_MAJOR_AR9344:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case REV_ID_MAJOR_QCA9533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case REV_ID_MAJOR_QCA9533_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case REV_ID_MAJOR_QCA9556:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case REV_ID_MAJOR_QCA9558:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case REV_ID_MAJOR_TP9343:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case REV_ID_MAJOR_QCA956X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) _prom_putchar = prom_putchar_ar71xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case REV_ID_MAJOR_AR9330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case REV_ID_MAJOR_AR9331:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) _prom_putchar = prom_putchar_ar933x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) _prom_putchar = prom_putchar_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) prom_enable_uart(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void prom_putchar(char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!_prom_putchar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) prom_putchar_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) _prom_putchar(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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