^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR71XX/AR724X/AR913X common routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static DEFINE_SPINLOCK(ath79_device_reset_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 ath79_cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXPORT_SYMBOL_GPL(ath79_cpu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 ath79_ahb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) EXPORT_SYMBOL_GPL(ath79_ahb_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 ath79_ddr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) EXPORT_SYMBOL_GPL(ath79_ddr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum ath79_soc_type ath79_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int ath79_soc_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *ath79_pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *ath79_reset_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXPORT_SYMBOL_GPL(ath79_reset_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __iomem *ath79_ddr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void __iomem *ath79_ddr_wb_flush_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void __iomem *ath79_ddr_pci_win_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void ath79_ddr_ctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) AR71XX_DDR_CTRL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ath79_ddr_pci_win_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void ath79_ddr_wb_flush(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Flush the DDR write buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writel(0x1, flush_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) while (__raw_readl(flush_reg) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* It must be run twice. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writel(0x1, flush_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) while (__raw_readl(flush_reg) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void ath79_ddr_set_pci_windows(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BUG_ON(!ath79_ddr_pci_win_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void ath79_device_reset_set(u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (soc_is_ar71xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg = AR71XX_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else if (soc_is_ar724x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg = AR724X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else if (soc_is_ar913x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = AR913X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else if (soc_is_ar933x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = AR933X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else if (soc_is_ar934x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = AR934X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else if (soc_is_qca953x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg = QCA953X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else if (soc_is_qca955x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = QCA955X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else if (soc_is_qca956x() || soc_is_tp9343())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg = QCA956X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_lock_irqsave(&ath79_device_reset_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) t = ath79_reset_rr(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ath79_reset_wr(reg, t | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXPORT_SYMBOL_GPL(ath79_device_reset_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void ath79_device_reset_clear(u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (soc_is_ar71xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = AR71XX_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else if (soc_is_ar724x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reg = AR724X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else if (soc_is_ar913x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg = AR913X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else if (soc_is_ar933x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg = AR933X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (soc_is_ar934x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = AR934X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else if (soc_is_qca953x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg = QCA953X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else if (soc_is_qca955x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = QCA955X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else if (soc_is_qca956x() || soc_is_tp9343())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg = QCA956X_RESET_REG_RESET_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_lock_irqsave(&ath79_device_reset_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) t = ath79_reset_rr(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ath79_reset_wr(reg, t & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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