^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR71XX/AR724X/AR913X common routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/ath79-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AR71XX_BASE_FREQ 40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AR724X_BASE_FREQ 40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct clk *clks[ATH79_CLK_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct clk_onecell_data clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .clks = clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .clk_num = ARRAY_SIZE(clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char * const clk_names[ATH79_CLK_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [ATH79_CLK_CPU] = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [ATH79_CLK_DDR] = "ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [ATH79_CLK_AHB] = "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [ATH79_CLK_REF] = "ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [ATH79_CLK_MDIO] = "mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char * __init ath79_clk_name(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return clk_names[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) panic("failed to allocate %s clock structure", clk_names[type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clks[type] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk_register_clkdev(clk, name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct clk * __init ath79_set_clk(int type, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const char *name = ath79_clk_name(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __ath79_set_clk(type, name, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int mult, unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char *name = ath79_clk_name(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __ath79_set_clk(type, name, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *clk = clks[ATH79_CLK_REF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk = ath79_set_clk(ATH79_CLK_REF, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void __init ar71xx_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long ddr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long ahb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) freq = div * ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cpu_rate = freq / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ddr_rate = freq / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ahb_rate = cpu_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void __init ar724x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 mult, div, ddr_div, ahb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ath79_setup_ref_clk(AR71XX_BASE_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void __init ar933x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 clock_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 ninit_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 out_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 cpu_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 ddr_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 ahb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (t & AR933X_BOOTSTRAP_REF_CLK_40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ref_rate = (40 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ref_rate = (25 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ath79_setup_ref_clk(ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ref_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ninit_mul = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) out_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cpu_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ddr_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ahb_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 cpu_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ref_div = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AR933X_PLL_CPU_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (t == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) t = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) out_div = (1 << t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ref_div * out_div * cpu_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ref_div * out_div * ddr_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ref_div * out_div * ahb_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 frac, u32 out_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) t = ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) t *= nint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) do_div(t, ref_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) t = ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) t *= nfrac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) do_div(t, ref_div * frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret += t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void __init ar934x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long ddr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long ahb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 cpu_pll, ddr_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __iomem *dpll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ref_rate = 40 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ref_rate = 25 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ref_rate = ath79_setup_ref_clk(ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AR934X_SRIF_DPLL2_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AR934X_SRIF_DPLL1_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) AR934X_SRIF_DPLL1_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) frac = 1 << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AR934X_PLL_CPU_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) frac = 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) nfrac, frac, out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) AR934X_SRIF_DPLL2_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AR934X_SRIF_DPLL1_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) AR934X_SRIF_DPLL1_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) frac = 1 << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) AR934X_PLL_DDR_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) frac = 1 << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) nfrac, frac, out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cpu_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cpu_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpu_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ddr_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ddr_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ddr_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ahb_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ahb_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ahb_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) iounmap(dpll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void __init qca953x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long ddr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long ahb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 cpu_pll, ddr_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ref_rate = 40 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ref_rate = 25 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ref_rate = ath79_setup_ref_clk(ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) QCA953X_PLL_CPU_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cpu_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cpu_pll += frac * (ref_rate >> 6) / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cpu_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) QCA953X_PLL_DDR_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ddr_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ddr_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cpu_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cpu_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cpu_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ddr_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ddr_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ddr_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ahb_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ahb_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ahb_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void __init qca955x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned long ddr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long ahb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 cpu_pll, ddr_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ref_rate = 40 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ref_rate = 25 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ref_rate = ath79_setup_ref_clk(ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) QCA955X_PLL_CPU_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cpu_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cpu_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) QCA955X_PLL_DDR_CONFIG_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ddr_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ddr_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cpu_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cpu_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cpu_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ddr_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ddr_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ddr_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ahb_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ahb_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ahb_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void __init qca956x_clocks_init(void __iomem *pll_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned long cpu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long ddr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long ahb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 cpu_pll, ddr_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * QCA956x timer init workaround has to be applied right before setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * up the clock. Else, there will be no jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ref_rate = 40 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ref_rate = 25 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ref_rate = ath79_setup_ref_clk(ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cpu_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cpu_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ddr_pll = nint * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ddr_pll /= (1 << out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cpu_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cpu_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cpu_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ddr_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ddr_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ddr_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ahb_rate = ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ahb_rate = ddr_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ahb_rate = cpu_pll / (postdiv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void __init ath79_clocks_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ref_clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!IS_ERR(ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clks[ATH79_CLK_REF] = ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pll_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!pll_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pr_err("%pOF: can't map pll registers\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (of_device_is_compatible(np, "qca,ar7100-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ar71xx_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) of_device_is_compatible(np, "qca,ar9130-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ar724x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else if (of_device_is_compatible(np, "qca,ar9330-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ar933x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else if (of_device_is_compatible(np, "qca,ar9340-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ar934x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) else if (of_device_is_compatible(np, "qca,qca9530-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) qca953x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else if (of_device_is_compatible(np, "qca,qca9550-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) qca955x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else if (of_device_is_compatible(np, "qca,qca9560-pll"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) qca956x_clocks_init(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!clks[ATH79_CLK_MDIO])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pr_err("%pOF: could not register clk provider\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) iounmap(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) clk_put(ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags