Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 FON Technology, SL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Platform devices for Atheros AR5312 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <ath25_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "ar5312.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "ar5312_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void __iomem *ar5312_rst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct irq_domain *ar5312_misc_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static inline u32 ar5312_rst_reg_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return __raw_readl(ar5312_rst_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline void ar5312_rst_reg_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	__raw_writel(val, ar5312_rst_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 ret = ar5312_rst_reg_read(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	ret |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ar5312_rst_reg_write(reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR);   /* clears error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		 proc_addr, proc1, dma_addr, dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	machine_restart("AHB error"); /* Catastrophic failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void ar5312_misc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		      ar5312_rst_reg_read(AR5312_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned nr, misc_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		struct irq_domain *domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		nr = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		misc_irq = irq_find_mapping(domain, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (misc_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		generic_handle_irq(misc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (nr == AR5312_MISC_IRQ_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			ar5312_rst_reg_read(AR5312_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* Enable the specified AR5312_MISC_IRQ interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void ar5312_misc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Disable the specified AR5312_MISC_IRQ interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void ar5312_misc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct irq_chip ar5312_misc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.name		= "ar5312-misc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.irq_unmask	= ar5312_misc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.irq_mask	= ar5312_misc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.map = ar5312_misc_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void ar5312_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 pending = read_c0_status() & read_c0_cause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (pending & CAUSEF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		do_IRQ(AR5312_IRQ_WLAN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	else if (pending & CAUSEF_IP5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		do_IRQ(AR5312_IRQ_WLAN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	else if (pending & CAUSEF_IP6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		do_IRQ(AR5312_IRQ_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	else if (pending & CAUSEF_IP7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		do_IRQ(ATH25_IRQ_CPU_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __init ar5312_arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ath25_irq_dispatch = ar5312_irq_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				       &ar5312_misc_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		panic("Failed to add IRQ domain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		pr_err("Failed to register ar5312-ahb-error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	irq_set_chained_handler_and_data(AR5312_IRQ_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					 ar5312_misc_irq_handler, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ar5312_misc_irq_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct physmap_flash_data ar5312_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct resource ar5312_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.start = AR5312_FLASH_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct platform_device ar5312_physmap_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.dev.platform_data = &ar5312_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.resource = &ar5312_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __init ar5312_flash_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	void __iomem *flashctl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	flashctl_base = ioremap(AR5312_FLASHCTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					AR5312_FLASHCTL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ctl &= AR5312_FLASHCTL_MW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* fixup flash width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	switch (ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case AR5312_FLASHCTL_MW16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		ar5312_flash_data.width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case AR5312_FLASHCTL_MW8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		ar5312_flash_data.width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * Configure flash bank 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * Assume 8M window size. Flash will be aliased if it's smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Disable other flash banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	iounmap(flashctl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __init ar5312_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct ath25_boarddata *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ar5312_flash_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Locate board/radio config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	config = ath25_board.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* AR2313 has CPU minor rev. 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if ((current_cpu_data.processor_id & 0xff) == 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		ath25_soc = ATH25_SOC_AR2313;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* AR2312 shares the same Silicon ID as AR5312 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	else if (config->flags & BD_ISCASPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ath25_soc = ATH25_SOC_AR2312;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Everything else is probably AR5312 or compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		ath25_soc = ATH25_SOC_AR5312;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	platform_device_register(&ar5312_physmap_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	switch (ath25_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case ATH25_SOC_AR5312:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (!ath25_board.radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (!(config->flags & BD_WLAN0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case ATH25_SOC_AR2312:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case ATH25_SOC_AR2313:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if (!ath25_board.radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (config->flags & BD_WLAN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void ar5312_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* reset the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * to determine the predevisor value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static unsigned __init ar5312_cpu_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u32 scratch, devid, clock_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	u32 predivide_mask, multiplier_mask, doubler_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	unsigned predivide_shift, multiplier_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	unsigned predivide_select, predivisor, multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* Trust the bootrom's idea of cpu frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	devid = ar5312_rst_reg_read(AR5312_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (devid == AR5312_REV_MAJ_AR2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	} else { /* AR5312 and AR2312 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 * Clocking is derived from a fixed 40MHz input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	 *  cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	 *  sys_freq = cpu_freq / 4	  (used for APB clock, serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	 *				   flash, Timer, Watchdog Timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 *  cnt_freq = cpu_freq / 2	  (use for CPU count/compare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 * So, for example, with a PLL multiplier of 5, we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	 *  cpu_freq = 200MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 *  sys_freq = 50MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 *  cnt_freq = 100MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 * We compute the CPU frequency, based on PLL settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	predivisor = clockctl1_predivide_table[predivide_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (clock_ctl1 & doubler_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		multiplier <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return (40000000 / predivisor) * multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static inline unsigned ar5312_sys_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return ar5312_cpu_frequency() / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void __init ar5312_plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mips_hpt_frequency = ar5312_cpu_frequency() / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void __init ar5312_plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	void __iomem *sdram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	u32 memsize, memcfg, bank0_ac, bank1_ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	u32 devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/* Detect memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	sdram_base = ioremap(AR5312_SDRAMCTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				     AR5312_SDRAMCTL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		  (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	memsize <<= 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	memblock_add(0, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	iounmap(sdram_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ar5312_rst_base = ioremap(AR5312_RST_BASE, AR5312_RST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	devid = ar5312_rst_reg_read(AR5312_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	devid >>= AR5312_REV_WMAC_MIN_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	devid &= AR5312_REV_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ath25_board.devid = (u16)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/* Clear any lingering AHB errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ar5312_rst_reg_read(AR5312_PROCADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ar5312_rst_reg_read(AR5312_DMAADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	_machine_restart = ar5312_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void __init ar5312_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 					  AR5312_MISC_IRQ_UART0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }