Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Register definitions for AR2315+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2006 FON Technology, SL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifndef __ASM_MACH_ATH25_AR2315_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define __ASM_MACH_ATH25_AR2315_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AR2315_IRQ_MISC		(MIPS_CPU_IRQ_BASE + 2)	/* C0_CAUSE: 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AR2315_IRQ_WLAN0	(MIPS_CPU_IRQ_BASE + 3)	/* C0_CAUSE: 0x0800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AR2315_IRQ_ENET0	(MIPS_CPU_IRQ_BASE + 4)	/* C0_CAUSE: 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AR2315_IRQ_LCBUS_PCI	(MIPS_CPU_IRQ_BASE + 5)	/* C0_CAUSE: 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AR2315_IRQ_WLAN0_POLL	(MIPS_CPU_IRQ_BASE + 6)	/* C0_CAUSE: 0x4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Miscellaneous interrupts, which share IP2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AR2315_MISC_IRQ_UART0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AR2315_MISC_IRQ_I2C_RSVD	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AR2315_MISC_IRQ_SPI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AR2315_MISC_IRQ_AHB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AR2315_MISC_IRQ_APB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AR2315_MISC_IRQ_TIMER		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AR2315_MISC_IRQ_GPIO		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AR2315_MISC_IRQ_WATCHDOG	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AR2315_MISC_IRQ_IR_RSVD		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AR2315_MISC_IRQ_COUNT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AR2315_SPI_READ_BASE	0x08000000	/* SPI flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AR2315_SPI_READ_SIZE	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AR2315_WLAN0_BASE	0x10000000	/* Wireless MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AR2315_PCI_BASE		0x10100000	/* PCI MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AR2315_PCI_SIZE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AR2315_SDRAMCTL_BASE	0x10300000	/* SDRAM MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AR2315_SDRAMCTL_SIZE	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AR2315_LOCAL_BASE	0x10400000	/* Local bus MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AR2315_ENET0_BASE	0x10500000	/* Ethernet MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AR2315_RST_BASE		0x11000000	/* Reset control MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AR2315_RST_SIZE		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AR2315_UART0_BASE	0x11100000	/* UART MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AR2315_SPI_MMR_BASE	0x11300000	/* SPI flash MMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AR2315_SPI_MMR_SIZE	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AR2315_PCI_EXT_BASE	0x80000000	/* PCI external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AR2315_PCI_EXT_SIZE	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * Configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Cold reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AR2315_COLD_RESET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AR2315_RESET_COLD_AHB		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AR2315_RESET_COLD_APB		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AR2315_RESET_COLD_CPU		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AR2315_RESET_COLD_CPUWARM	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AR2315_RESET_SYSTEM		(RESET_COLD_CPU |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					 RESET_COLD_APB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					 RESET_COLD_AHB)  /* full system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AR2317_RESET_SYSTEM		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AR2315_RESET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AR2315_RESET_WARM_WLAN0_MAC	0x00000001  /* warm reset WLAN0 MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AR2315_RESET_WARM_WLAN0_BB	0x00000002  /* warm reset WLAN0 BB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AR2315_RESET_MPEGTS_RSVD	0x00000004  /* warm reset MPEG-TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AR2315_RESET_PCIDMA		0x00000008  /* warm reset PCI ahb/dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AR2315_RESET_MEMCTL		0x00000010  /* warm reset mem control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AR2315_RESET_LOCAL		0x00000020  /* warm reset local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AR2315_RESET_I2C_RSVD		0x00000040  /* warm reset I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AR2315_RESET_SPI		0x00000080  /* warm reset SPI iface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AR2315_RESET_UART0		0x00000100  /* warm reset UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AR2315_RESET_IR_RSVD		0x00000200  /* warm reset IR iface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define AR2315_RESET_EPHY0		0x00000400  /* cold reset ENET0 phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AR2315_RESET_ENET0		0x00000800  /* cold reset ENET0 MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* AHB master arbitration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AR2315_AHB_ARB_CTL		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AR2315_ARB_CPU			0x00000001  /* CPU, default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define AR2315_ARB_WLAN			0x00000002  /* WLAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AR2315_ARB_MPEGTS_RSVD		0x00000004  /* MPEG-TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AR2315_ARB_LOCAL		0x00000008  /* Local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AR2315_ARB_PCI			0x00000010  /* PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AR2315_ARB_ETHERNET		0x00000020  /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AR2315_ARB_RETRY		0x00000100  /* Retry policy (debug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AR2315_ENDIAN_CTL		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AR2315_CONFIG_AHB		0x00000001  /* EC-AHB bridge endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AR2315_CONFIG_WLAN		0x00000002  /* WLAN byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AR2315_CONFIG_MPEGTS_RSVD	0x00000004  /* MPEG-TS byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AR2315_CONFIG_PCI		0x00000008  /* PCI byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AR2315_CONFIG_MEMCTL		0x00000010  /* Mem controller endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AR2315_CONFIG_LOCAL		0x00000020  /* Local bus byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AR2315_CONFIG_ETHERNET		0x00000040  /* Ethernet byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AR2315_CONFIG_MERGE		0x00000200  /* CPU write buffer merge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AR2315_CONFIG_CPU		0x00000400  /* CPU big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AR2315_CONFIG_BIG		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AR2315_CONFIG_PCIAHB		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AR2315_CONFIG_PCIAHB_BRIDGE	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AR2315_CONFIG_SPI		0x00008000  /* SPI byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AR2315_CONFIG_CPU_DRAM		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AR2315_CONFIG_CPU_PCI		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AR2315_CONFIG_CPU_MMR		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* NMI control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AR2315_NMI_CTL			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AR2315_NMI_EN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AR2315_SREV			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AR2315_REV_MAJ			0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AR2315_REV_MAJ_S		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AR2315_REV_MIN			0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AR2315_REV_MIN_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AR2315_REV_CHIP			(AR2315_REV_MAJ | AR2315_REV_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Interface Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AR2315_IF_CTL			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AR2315_IF_MASK			0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AR2315_IF_DISABLED		0		/* Disable all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AR2315_IF_PCI			1		/* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AR2315_IF_TS_LOCAL		2		/* Local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AR2315_IF_ALL			3		/* Emulation only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AR2315_IF_LOCAL_HOST		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AR2315_IF_PCI_HOST		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AR2315_IF_PCI_INTR		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AR2315_IF_PCI_CLK_MASK		0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AR2315_IF_PCI_CLK_INPUT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AR2315_IF_PCI_CLK_OUTPUT_LOW	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AR2315_IF_PCI_CLK_OUTPUT_CLK	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AR2315_IF_PCI_CLK_OUTPUT_HIGH	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AR2315_IF_PCI_CLK_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* APB Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AR2315_ISR			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AR2315_IMR			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AR2315_GISR			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AR2315_ISR_UART0	0x00000001	/* high speed UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AR2315_ISR_I2C_RSVD	0x00000002	/* I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AR2315_ISR_SPI		0x00000004	/* SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AR2315_ISR_AHB		0x00000008	/* AHB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AR2315_ISR_APB		0x00000010	/* APB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AR2315_ISR_TIMER	0x00000020	/* Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AR2315_ISR_GPIO		0x00000040	/* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AR2315_ISR_WD		0x00000080	/* Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AR2315_ISR_IR_RSVD	0x00000100	/* IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AR2315_GISR_MISC	0x00000001	/* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AR2315_GISR_WLAN0	0x00000002	/* WLAN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AR2315_GISR_MPEGTS_RSVD	0x00000004	/* MPEG-TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AR2315_GISR_LOCALPCI	0x00000008	/* Local/PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AR2315_GISR_WMACPOLL	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AR2315_GISR_TIMER	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AR2315_GISR_ETHERNET	0x00000040	/* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Generic timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AR2315_TIMER			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AR2315_RELOAD			0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AR2315_WDT_TIMER		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AR2315_WDT_CTRL			0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AR2315_WDT_CTRL_IGNORE	0x00000000	/* ignore expiration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AR2315_WDT_CTRL_NMI	0x00000001	/* NMI on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AR2315_WDT_CTRL_RESET	0x00000002	/* reset on watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* CPU Performance Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AR2315_PERFCNT0			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AR2315_PERFCNT1			0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AR2315_PERF0_DATAHIT	0x00000001  /* Count Data Cache Hits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AR2315_PERF0_DATAMISS	0x00000002  /* Count Data Cache Misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AR2315_PERF0_INSTHIT	0x00000004  /* Count Instruction Cache Hits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AR2315_PERF0_INSTMISS	0x00000008  /* Count Instruction Cache Misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AR2315_PERF0_ACTIVE	0x00000010  /* Count Active Processor Cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AR2315_PERF0_WBHIT	0x00000020  /* Count CPU Write Buffer Hits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AR2315_PERF0_WBMISS	0x00000040  /* Count CPU Write Buffer Misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AR2315_PERF1_EB_ARDY	0x00000001  /* Count EB_ARdy signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AR2315_PERF1_EB_AVALID	0x00000002  /* Count EB_AValid signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AR2315_PERF1_EB_WDRDY	0x00000004  /* Count EB_WDRdy signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AR2315_PERF1_EB_RDVAL	0x00000008  /* Count EB_RdVal signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AR2315_PERF1_VRADDR	0x00000010  /* Count valid read address cycles*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AR2315_PERF1_VWADDR	0x00000020  /* Count valid write address cycl.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AR2315_PERF1_VWDATA	0x00000040  /* Count valid write data cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* AHB Error Reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AR2315_AHB_ERR0			0x0050  /* error  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AR2315_AHB_ERR1			0x0054  /* haddr  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AR2315_AHB_ERR2			0x0058  /* hwdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AR2315_AHB_ERR3			0x005c  /* hrdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AR2315_AHB_ERR4			0x0060  /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AR2315_AHB_ERROR_DET	1 /* AHB Error has been detected,          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				  /* write 1 to clear all bits in ERR0     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AR2315_AHB_ERROR_OVR	2 /* AHB Error overflow has been detected  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AR2315_AHB_ERROR_WDT	4 /* AHB Error due to wdt instead of hresp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AR2315_PROCERR_HMAST		0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AR2315_PROCERR_HMAST_DFLT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AR2315_PROCERR_HMAST_WMAC	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AR2315_PROCERR_HMAST_ENET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AR2315_PROCERR_HMAST_PCIENDPT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AR2315_PROCERR_HMAST_LOCAL	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AR2315_PROCERR_HMAST_CPU	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AR2315_PROCERR_HMAST_PCITGT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AR2315_PROCERR_HMAST_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AR2315_PROCERR_HWRITE		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AR2315_PROCERR_HSIZE		0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AR2315_PROCERR_HSIZE_S		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AR2315_PROCERR_HTRANS		0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AR2315_PROCERR_HTRANS_S		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AR2315_PROCERR_HBURST		0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AR2315_PROCERR_HBURST_S		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Clock Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AR2315_PLLC_CTL			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AR2315_PLLV_CTL			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AR2315_CPUCLK			0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AR2315_AMBACLK			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AR2315_SYNCCLK			0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AR2315_DSL_SLEEP_CTL		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AR2315_DSL_SLEEP_DUR		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* PLLc Control fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AR2315_PLLC_REF_DIV_M		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AR2315_PLLC_REF_DIV_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AR2315_PLLC_FDBACK_DIV_M	0x0000007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AR2315_PLLC_FDBACK_DIV_S	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AR2315_PLLC_ADD_FDBACK_DIV_M	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AR2315_PLLC_ADD_FDBACK_DIV_S	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AR2315_PLLC_CLKC_DIV_M		0x0001c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AR2315_PLLC_CLKC_DIV_S		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AR2315_PLLC_CLKM_DIV_M		0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AR2315_PLLC_CLKM_DIV_S		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* CPU CLK Control fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AR2315_CPUCLK_CLK_SEL_M		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AR2315_CPUCLK_CLK_SEL_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AR2315_CPUCLK_CLK_DIV_M		0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AR2315_CPUCLK_CLK_DIV_S		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* AMBA CLK Control fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AR2315_AMBACLK_CLK_SEL_M	0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AR2315_AMBACLK_CLK_SEL_S	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AR2315_AMBACLK_CLK_DIV_M	0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AR2315_AMBACLK_CLK_DIV_S	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* PCI Clock Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AR2315_PCICLK			0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define AR2315_PCICLK_INPUT_M		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AR2315_PCICLK_INPUT_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AR2315_PCICLK_PLLC_CLKM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AR2315_PCICLK_PLLC_CLKM1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AR2315_PCICLK_PLLC_CLKC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AR2315_PCICLK_REF_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define AR2315_PCICLK_DIV_M		0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AR2315_PCICLK_DIV_S		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AR2315_PCICLK_IN_FREQ		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AR2315_PCICLK_IN_FREQ_DIV_6	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AR2315_PCICLK_IN_FREQ_DIV_8	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AR2315_PCICLK_IN_FREQ_DIV_10	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Observation Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AR2315_OCR			0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AR2315_OCR_GPIO0_IRIN		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AR2315_OCR_GPIO1_IROUT		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define AR2315_OCR_GPIO3_RXCLR		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* General Clock Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define AR2315_MISCCLK			0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define AR2315_MISCCLK_PLLBYPASS_EN	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AR2315_MISCCLK_PROCREFCLK	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * SDRAM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *   - No read or write buffers are included.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define AR2315_MEM_CFG			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define AR2315_MEM_CTRL			0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AR2315_MEM_REF			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AR2315_MEM_CFG_DATA_WIDTH_M	0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AR2315_MEM_CFG_DATA_WIDTH_S	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AR2315_MEM_CFG_COL_WIDTH_M	0x00001e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define AR2315_MEM_CFG_COL_WIDTH_S	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AR2315_MEM_CFG_ROW_WIDTH_M	0x000001e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AR2315_MEM_CFG_ROW_WIDTH_S	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AR2315_MEM_CFG_BANKADDR_BITS_M	0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define AR2315_MEM_CFG_BANKADDR_BITS_S	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * Local Bus Interface Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AR2315_LB_CONFIG		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AR2315_LBCONF_OE	0x00000001	/* =1 OE is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define AR2315_LBCONF_CS0	0x00000002	/* =1 first CS is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define AR2315_LBCONF_CS1	0x00000004	/* =1 2nd CS is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define AR2315_LBCONF_RDY	0x00000008	/* =1 RDY is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define AR2315_LBCONF_WE	0x00000010	/* =1 Write En is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define AR2315_LBCONF_WAIT	0x00000020	/* =1 WAIT is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AR2315_LBCONF_ADS	0x00000040	/* =1 Adr Strobe is low-true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define AR2315_LBCONF_MOT	0x00000080	/* =0 Intel, =1 Motorola */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AR2315_LBCONF_8CS	0x00000100	/* =1 8 bits CS, 0= 16bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AR2315_LBCONF_8DS	0x00000200	/* =1 8 bits Data S, 0=16bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AR2315_LBCONF_ADS_EN	0x00000400	/* =1 Enable ADS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define AR2315_LBCONF_ADR_OE	0x00000800	/* =1 Adr cap on OE, WE or DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AR2315_LBCONF_ADDT_MUX	0x00001000	/* =1 Adr and Data share bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define AR2315_LBCONF_DATA_OE	0x00002000	/* =1 Data cap on OE, WE, DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AR2315_LBCONF_16DATA	0x00004000	/* =1 Data is 16 bits wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define AR2315_LBCONF_SWAPDT	0x00008000	/* =1 Byte swap data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define AR2315_LBCONF_SYNC	0x00010000	/* =1 Bus synchronous to clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define AR2315_LBCONF_INT	0x00020000	/* =1 Intr is low true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AR2315_LBCONF_INT_CTR0	0x00000000	/* GND high-Z, Vdd is high-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AR2315_LBCONF_INT_CTR1	0x00040000	/* GND drive, Vdd is high-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AR2315_LBCONF_INT_CTR2	0x00080000	/* GND high-Z, Vdd drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AR2315_LBCONF_INT_CTR3	0x000c0000	/* GND drive, Vdd drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define AR2315_LBCONF_RDY_WAIT	0x00100000	/* =1 RDY is negative of WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AR2315_LBCONF_INT_PULSE	0x00200000	/* =1 Interrupt is a pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AR2315_LBCONF_ENABLE	0x00400000	/* =1 Falcon respond to LB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AR2315_LB_CLKSEL		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AR2315_LBCLK_EXT	0x00000001	/* use external clk for lb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define AR2315_LB_1MS			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define AR2315_LB1MS_MASK	0x0003ffff	/* # of AHB clk cycles in 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AR2315_LB_MISCCFG		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define AR2315_LBM_TXD_EN	0x00000001	/* Enable TXD for fragments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AR2315_LBM_RX_INTEN	0x00000002	/* Enable LB ints on RX ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AR2315_LBM_MBOXWR_INTEN	0x00000004	/* Enable LB ints on mbox wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AR2315_LBM_MBOXRD_INTEN	0x00000008	/* Enable LB ints on mbox rd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AR2315_LMB_DESCSWAP_EN	0x00000010	/* Byte swap desc enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define AR2315_LBM_TIMEOUT_M	0x00ffff80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AR2315_LBM_TIMEOUT_S	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define AR2315_LBM_PORTMUX	0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define AR2315_LB_RXTSOFF		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define AR2315_LB_TX_CHAIN_EN		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AR2315_LB_TXEN_0	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AR2315_LB_TXEN_1	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AR2315_LB_TXEN_2	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define AR2315_LB_TXEN_3	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define AR2315_LB_TX_CHAIN_DIS		0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define AR2315_LB_TX_DESC_PTR		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define AR2315_LB_RX_CHAIN_EN		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define AR2315_LB_RXEN		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define AR2315_LB_RX_CHAIN_DIS		0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define AR2315_LB_RX_DESC_PTR		0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define AR2315_LB_INT_STATUS		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define AR2315_LB_INT_TX_DESC		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define AR2315_LB_INT_TX_OK		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define AR2315_LB_INT_TX_ERR		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define AR2315_LB_INT_TX_EOF		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AR2315_LB_INT_RX_DESC		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AR2315_LB_INT_RX_OK		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define AR2315_LB_INT_RX_ERR		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define AR2315_LB_INT_RX_EOF		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define AR2315_LB_INT_TX_TRUNC		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AR2315_LB_INT_TX_STARVE		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define AR2315_LB_INT_LB_TIMEOUT	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define AR2315_LB_INT_LB_ERR		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AR2315_LB_INT_MBOX_WR		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define AR2315_LB_INT_MBOX_RD		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Bit definitions for INT MASK are the same as INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define AR2315_LB_INT_MASK		0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define AR2315_LB_INT_EN		0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define AR2315_LB_MBOX			0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif /* __ASM_MACH_ATH25_AR2315_REGS_H */