Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 FON Technology, SL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Platform devices for Atheros AR2315 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <ath25_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "ar2315.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "ar2315_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static void __iomem *ar2315_rst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct irq_domain *ar2315_misc_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static inline u32 ar2315_rst_reg_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return __raw_readl(ar2315_rst_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static inline void ar2315_rst_reg_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	__raw_writel(val, ar2315_rst_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 ret = ar2315_rst_reg_read(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ret |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	ar2315_rst_reg_write(reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ar2315_rst_reg_read(AR2315_AHB_ERR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	pr_emerg("AHB fatal error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	machine_restart("AHB error"); /* Catastrophic failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void ar2315_misc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		      ar2315_rst_reg_read(AR2315_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned nr, misc_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		struct irq_domain *domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		nr = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		misc_irq = irq_find_mapping(domain, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (misc_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (nr == AR2315_MISC_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		else if (nr == AR2315_MISC_IRQ_WATCHDOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		generic_handle_irq(misc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void ar2315_misc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void ar2315_misc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct irq_chip ar2315_misc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.name		= "ar2315-misc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.irq_unmask	= ar2315_misc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.irq_mask	= ar2315_misc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.map = ar2315_misc_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Called when an interrupt is received, this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * determines exactly which interrupt it was, and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * invokes the appropriate handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * Implicitly, we also define interrupt priority by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * choosing which to dispatch first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void ar2315_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 pending = read_c0_status() & read_c0_cause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (pending & CAUSEF_IP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		do_IRQ(AR2315_IRQ_WLAN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_PCI_AR2315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	else if (pending & CAUSEF_IP5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		do_IRQ(AR2315_IRQ_LCBUS_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else if (pending & CAUSEF_IP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		do_IRQ(AR2315_IRQ_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	else if (pending & CAUSEF_IP7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		do_IRQ(ATH25_IRQ_CPU_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __init ar2315_arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ath25_irq_dispatch = ar2315_irq_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				       &ar2315_misc_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		panic("Failed to add IRQ domain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pr_err("Failed to register ar2315-ahb-error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					 ar2315_misc_irq_handler, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ar2315_misc_irq_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init ar2315_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Find board configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void ar2315_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	void (*mips_reset_vec)(void) = (void *)0xbfc00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* try reset the system via reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Cold reset does not work on the AR2315/6, use the GPIO reset bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * a workaround. Give it some time to attempt a gpio based hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * reset (atheros reference design workaround) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* TODO: implement the GPIO reset workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * workaround. Attempt to jump to the mips reset location -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * the boot loader itself might be able to recover the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mips_reset_vec();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * to determine the predevisor value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static unsigned __init ar2315_sys_clk(u32 clock_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned int pllc_ctrl, cpu_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned int pllc_out, refdiv, fdiv, divby2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	refdiv = clockctl1_predivide_table[refdiv];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* clkm input selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		clk_div = pllc_divide_table[clk_div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		clk_div = pllc_divide_table[clk_div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		pllc_out = 40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		clk_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	cpu_div = cpu_div * 2 ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return pllc_out / (clk_div * cpu_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline unsigned ar2315_cpu_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline unsigned ar2315_apb_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void __init ar2315_plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mips_hpt_frequency = ar2315_cpu_frequency() / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __init ar2315_plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	void __iomem *sdram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32 memsize, memcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u32 devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Detect memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	sdram_base = ioremap(AR2315_SDRAMCTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				     AR2315_SDRAMCTL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	memsize   = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	memsize <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	memblock_add(0, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	iounmap(sdram_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Detect the hardware based on the device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	switch (devid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	case 0x91:	/* Need to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		ath25_soc = ATH25_SOC_AR2318;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case 0x90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ath25_soc = ATH25_SOC_AR2317;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case 0x87:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		ath25_soc = ATH25_SOC_AR2316;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case 0x86:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		ath25_soc = ATH25_SOC_AR2315;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ath25_board.devid = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* Clear any lingering AHB errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	config = read_c0_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	write_c0_config(config & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ar2315_rst_reg_read(AR2315_AHB_ERR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	_machine_restart = ar2315_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifdef CONFIG_PCI_AR2315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct resource ar2315_pci_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.name = "ar2315-pci-ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.start = AR2315_PCI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.name = "ar2315-pci-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.start = AR2315_PCI_EXT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.name = "ar2315-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.start = AR2315_IRQ_LCBUS_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.end = AR2315_IRQ_LCBUS_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __init ar2315_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 					  AR2315_MISC_IRQ_UART0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_PCI_AR2315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (ath25_soc == ATH25_SOC_AR2315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		/* Reset PCI DMA logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		/* Configure endians */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				    AR2315_CONFIG_PCIAHB_BRIDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		/* Configure as PCI host with DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				  (AR2315_PCICLK_IN_FREQ_DIV_6 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				   AR2315_PCICLK_DIV_S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				    AR2315_IF_MASK, AR2315_IF_PCI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				    AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				    (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				     AR2315_IF_PCI_CLK_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		platform_device_register_simple("ar2315-pci", -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 						ar2315_pci_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 						ARRAY_SIZE(ar2315_pci_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }