^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach-ar7/ar7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach-ar7/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static void ar7_machine_restart(char *command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) writel(1, softres_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void ar7_machine_halt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void ar7_machine_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 power_state = readl(power_reg) | (3 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) writel(power_state, power_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ar7_machine_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 chip_id = ar7_chip_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 titan_variant_id = titan_chip_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case AR7_CHIP_7100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return "TI AR7 (TNETD7100)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case AR7_CHIP_7200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return "TI AR7 (TNETD7200)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case AR7_CHIP_7300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return "TI AR7 (TNETD7300)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case AR7_CHIP_TITAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) switch (titan_variant_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case TITAN_CHIP_1050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return "TI AR7 (TNETV1050)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case TITAN_CHIP_1055:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return "TI AR7 (TNETV1055)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case TITAN_CHIP_1056:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return "TI AR7 (TNETV1056)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case TITAN_CHIP_1060:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return "TI AR7 (TNETV1060)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return "TI AR7 (unknown)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int __init ar7_init_console(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) console_initcall(ar7_init_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Initializes basic routines and structures pointers, memory size (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * given by the bios and saves the command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _machine_restart = ar7_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) _machine_halt = ar7_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pm_power_off = ar7_machine_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) panic("Can't remap IO base!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) set_io_port_base(io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) prom_meminit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) get_system_type(), ar7_chip_id(), ar7_chip_rev());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }