^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach-ar7/ar7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EXCEPT_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PACE_OFFSET 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CHNLS_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIR_OFFSET (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSR_OFFSET (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int ar7_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void ar7_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) writel(1 << ((d->irq - ar7_irq_base) % 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) REG(ESR_OFFSET(d->irq - ar7_irq_base)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void ar7_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writel(1 << ((d->irq - ar7_irq_base) % 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) REG(ECR_OFFSET(d->irq - ar7_irq_base)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void ar7_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel(1 << ((d->irq - ar7_irq_base) % 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) REG(CR_OFFSET(d->irq - ar7_irq_base)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void ar7_unmask_sec_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void ar7_mask_sec_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void ar7_ack_sec_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct irq_chip ar7_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "AR7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .irq_unmask = ar7_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .irq_mask = ar7_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .irq_ack = ar7_ack_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct irq_chip ar7_sec_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "AR7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .irq_unmask = ar7_unmask_sec_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .irq_mask = ar7_mask_sec_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_ack = ar7_ack_sec_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init ar7_irq_init(int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Disable interrupts and clear pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel(0xffffffff, REG(ECR_OFFSET(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(0xff, REG(ECR_OFFSET(32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(0xffffffff, REG(SEC_ECR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(0xffffffff, REG(CR_OFFSET(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(0xff, REG(CR_OFFSET(32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(0xffffffff, REG(SEC_CR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ar7_irq_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) for (i = 0; i < 40; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(i, REG(CHNL_OFFSET(i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Primary IRQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_set_chip_and_handler(base + i, &ar7_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Secondary IRQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (i < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irq_set_chip_and_handler(base + i + 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) &ar7_sec_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "AR7 cascade interrupt", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ar7_irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) set_c0_status(IE_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ar7_irq_init(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void ar7_cascade(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Primary IRQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irq = readl(REG(PIR_OFFSET)) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) do_IRQ(ar7_irq_base + irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Secondary IRQ's are cascaded through primary '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(1, REG(CR_OFFSET(irq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) status = readl(REG(SEC_SR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (status & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) do_IRQ(ar7_irq_base + i + 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) status >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pending & STATUSF_IP7) /* cpu timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) do_IRQ(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else if (pending & STATUSF_IP2) /* int0 hardware line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ar7_cascade();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags