^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach-ar7/ar7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BOOT_PLL_SOURCE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_PLL_SOURCE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BUS_PLL_SOURCE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USB_PLL_SOURCE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DSP_PLL_SOURCE_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BOOT_PLL_SOURCE_AFE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BOOT_PLL_SOURCE_BUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BOOT_PLL_SOURCE_REF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BOOT_PLL_SOURCE_XTAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BOOT_PLL_SOURCE_CPU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BOOT_PLL_BYPASS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BOOT_PLL_ASYNC_MODE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BOOT_PLL_2TO1_MODE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TNETD7200_CLOCK_ID_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TNETD7200_CLOCK_ID_DSP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TNETD7200_CLOCK_ID_USB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TNETD7200_DEF_CPU_CLK 211000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TNETD7200_DEF_DSP_CLK 125000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TNETD7200_DEF_USB_CLK 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tnetd7300_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PREDIV_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PREDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define POSTDIV_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 unused1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MUL_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MUL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLL_MODE_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLL_NDIV 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLL_DIV 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLL_STATUS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 unused2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct tnetd7300_clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct tnetd7300_clock bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct tnetd7300_clock cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct tnetd7300_clock usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct tnetd7300_clock dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct tnetd7200_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 unused1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DIVISOR_ENABLE_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 postdiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 unused2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 cmden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 padding[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct tnetd7200_clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct tnetd7200_clock cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct tnetd7200_clock dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct tnetd7200_clock usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct clk bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .rate = 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct clk cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .rate = 150000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clk dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct clk vbus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void approximate(int base, int target, int *prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int *postdiv, int *mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int i, j, k, freq, res = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 1; i <= 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (j = 1; j <= 32; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for (k = 1; k <= 32; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) freq = abs(base / j * i / k - target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (freq < res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) res = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *mul = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *prediv = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *postdiv = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void calculate(int base, int target, int *prediv, int *postdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int *mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int tmp_gcd, tmp_base, tmp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (*prediv = 1; *prediv <= 32; (*prediv)++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tmp_base = base / *prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tmp_gcd = gcd(target, tmp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *mul = target / tmp_gcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *postdiv = tmp_base / tmp_gcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if ((*mul < 1) || (*mul >= 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if ((*postdiv > 0) & (*postdiv <= 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (base / *prediv * *mul / *postdiv != target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) approximate(base, target, prediv, postdiv, mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tmp_freq = base / *prediv * *mul / *postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "Adjusted requested frequency %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) target, tmp_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *prediv, *postdiv, *mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int tnetd7300_dsp_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 didr1, didr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 rev = ar7_chip_rev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (didr2 & (1 << 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((rev >= 0x23) && (rev != 0x57))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) > 4208000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 *bootcr, u32 bus_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int base_clock = AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 ctrl = readl(&clock->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 pll = readl(&clock->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int postdiv = (ctrl & POSTDIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int divisor = prediv * postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case BOOT_PLL_SOURCE_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) base_clock = bus_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case BOOT_PLL_SOURCE_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) base_clock = AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case BOOT_PLL_SOURCE_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) base_clock = AR7_XTAL_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case BOOT_PLL_SOURCE_CPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) base_clock = cpu_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (*bootcr & BOOT_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return base_clock / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((pll & PLL_MODE_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return (base_clock >> (mul / 16 + 1)) / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) product = (mul & 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (base_clock * mul) >> 1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (base_clock * (mul - 1)) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return product / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (mul == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return base_clock / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return base_clock * mul / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 *bootcr, u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int prediv, postdiv, mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int base_clock = bus_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case BOOT_PLL_SOURCE_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) base_clock = bus_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case BOOT_PLL_SOURCE_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) base_clock = AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case BOOT_PLL_SOURCE_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) base_clock = AR7_XTAL_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case BOOT_PLL_SOURCE_CPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) base_clock = cpu_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) calculate(base_clock, frequency, &prediv, &postdiv, &mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(4, &clock->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) while (readl(&clock->pll) & PLL_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mdelay(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __init tnetd7300_init_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct tnetd7300_clocks *clocks =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ioremap(UR8_REGS_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sizeof(struct tnetd7300_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) &clocks->bus, bootcr, AR7_AFE_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (*bootcr & BOOT_PLL_ASYNC_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &clocks->cpu, bootcr, AR7_AFE_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cpu_clk.rate = bus_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (dsp_clk.rate == 250000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bootcr, dsp_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) iounmap(clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iounmap(bootcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "Clocks: base = %d, frequency = %u, prediv = %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "postdiv = %d, postdiv2 = %d, mul = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) base, frequency, prediv, postdiv, postdiv2, mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(0, &clock->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel((mul - 1) & 0xF, &clock->mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) while (readl(&clock->status) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ; /* nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(readl(&clock->cmden) | 1, &clock->cmden);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(readl(&clock->cmd) | 1, &clock->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) while (readl(&clock->status) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ; /* nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(readl(&clock->cmden) | 1, &clock->cmden);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(readl(&clock->cmd) | 1, &clock->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) while (readl(&clock->status) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ; /* nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(readl(&clock->ctrl) | 1, &clock->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (*bootcr & BOOT_PLL_ASYNC_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Async */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) switch (clock_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case TNETD7200_CLOCK_ID_DSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return AR7_AFE_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (*bootcr & BOOT_PLL_2TO1_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* 2:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (clock_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case TNETD7200_CLOCK_ID_DSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return AR7_AFE_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* 1:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return AR7_REF_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void __init tnetd7200_init_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct tnetd7200_clocks *clocks =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ioremap(AR7_REGS_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sizeof(struct tnetd7200_clocks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int usb_base, usb_mul, usb_prediv, usb_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (*bootcr & BOOT_PLL_ASYNC_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) printk(KERN_INFO "Clocks: Async mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) printk(KERN_INFO "Clocks: Setting DSP clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &dsp_prediv, &dsp_postdiv, &dsp_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bus_clk.rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tnetd7200_set_clock(dsp_base, &clocks->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bus_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) printk(KERN_INFO "Clocks: Setting CPU clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &cpu_postdiv, &cpu_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cpu_clk.rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tnetd7200_set_clock(cpu_base, &clocks->cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cpu_prediv, cpu_postdiv, -1, cpu_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cpu_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (*bootcr & BOOT_PLL_2TO1_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) printk(KERN_INFO "Clocks: Setting CPU clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) &cpu_postdiv, &cpu_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) / cpu_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tnetd7200_set_clock(cpu_base, &clocks->cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cpu_prediv, cpu_postdiv, -1, cpu_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cpu_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) printk(KERN_INFO "Clocks: Setting DSP clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &dsp_postdiv, &dsp_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bus_clk.rate = cpu_clk.rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tnetd7200_set_clock(dsp_base, &clocks->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dsp_mul * 2, bus_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) printk(KERN_INFO "Clocks: Setting DSP clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) &dsp_postdiv, &dsp_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) / dsp_postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tnetd7200_set_clock(dsp_base, &clocks->dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dsp_mul * 2, bus_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cpu_clk.rate = bus_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) printk(KERN_INFO "Clocks: Setting USB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) usb_base = bus_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &usb_postdiv, &usb_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tnetd7200_set_clock(usb_base, &clocks->usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) usb_prediv, usb_postdiv, -1, usb_mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) TNETD7200_DEF_USB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dsp_clk.rate = cpu_clk.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) iounmap(clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) iounmap(bootcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Linux clock API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int clk_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EXPORT_SYMBOL(clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void clk_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) EXPORT_SYMBOL(clk_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long clk_get_rate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) EXPORT_SYMBOL(clk_get_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct clk *clk_get(struct device *dev, const char *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!strcmp(id, "bus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return &bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* cpmac and vbus share the same rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!strcmp(id, "cpmac"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return &vbus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!strcmp(id, "cpu"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return &cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!strcmp(id, "dsp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return &dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!strcmp(id, "vbus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return &vbus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) EXPORT_SYMBOL(clk_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void clk_put(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) EXPORT_SYMBOL(clk_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __init ar7_init_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) switch (ar7_chip_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case AR7_CHIP_7100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case AR7_CHIP_7200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) tnetd7200_init_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case AR7_CHIP_7300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dsp_clk.rate = tnetd7300_dsp_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tnetd7300_init_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* adjust vbus clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) vbus_clk.rate = bus_clk.rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* dummy functions, should not be called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) long clk_round_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) WARN_ON(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) EXPORT_SYMBOL(clk_round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int clk_set_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) WARN_ON(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL(clk_set_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int clk_set_parent(struct clk *clk, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) WARN_ON(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) EXPORT_SYMBOL(clk_set_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct clk *clk_get_parent(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) WARN_ON(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) EXPORT_SYMBOL(clk_get_parent);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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