^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DBAu1300 init and platform device setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio_keys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/input.h> /* KEY_* codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/wm97xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach-au1x00/gpio-au1300.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach-au1x00/au1100_mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-au1x00/au1200fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach-au1x00/au1xxx_dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach-au1x00/au1xxx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-db1x00/bcsr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach-au1x00/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* FPGA (external mux) interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DB1300_CF_INT (DB1300_FIRST_INT + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DB1300_DC_INT (DB1300_FIRST_INT + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* SMSC9210 CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DB1300_ETH_PHYS_ADDR 0x19000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DB1300_ETH_PHYS_END 0x197fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* ATA CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DB1300_IDE_PHYS_ADDR 0x18800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DB1300_IDE_REG_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* NAND CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DB1300_NAND_PHYS_ADDR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DB1300_NAND_PHYS_END 0x20000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct i2c_board_info db1300_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* multifunction pins to assign to GPIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int db1300_gpio_pins[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AU1300_PIN_EXTCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) -1, /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* multifunction pins to assign to device functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int db1300_dev_pins[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* wake-from-str pins 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) AU1300_PIN_WAKE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* external clock sources for PSC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) AU1300_PIN_EXTCLK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 8bit MMC interface on SD0: 6-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AU1300_PIN_SD0DAT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* UART1 pins: 11-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AU1300_PIN_U1RX, AU1300_PIN_U1TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* UART0 pins: 19-24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* UART2: 25-26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AU1300_PIN_U2RX, AU1300_PIN_U2TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* UART3: 27-28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AU1300_PIN_U3RX, AU1300_PIN_U3TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* LCD controller PWMs, ext pixclock: 30-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SD1 interface: 32-37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* SD2 interface: 38-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* PSC0/1 clocks: 44-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* PSCs: 46-49/50-53/54-57/58-61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AU1300_PIN_PSC0D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AU1300_PIN_PSC1D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AU1300_PIN_PSC2D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AU1300_PIN_PSC3D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* PCMCIA interface: 62-70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* camera interface H/V sync inputs: 71-72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* PSC2/3 clocks: 73-74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) -1, /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void __init db1300_gpio_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int *i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) i = &db1300_dev_pins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) while (*i != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) au1300_pinfunc_to_dev(*i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) i = &db1300_gpio_pins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) while (*i != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u64 au1300_all_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void au1300_nand_cmd_ctrl(struct nand_chip *this, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ioaddr &= 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ctrl & NAND_CLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ioaddr += MEM_STNAND_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else if (ctrl & NAND_ALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ioaddr += MEM_STNAND_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* assume we want to r/w real data by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ioaddr += MEM_STNAND_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (cmd != NAND_CMD_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __raw_writeb(cmd, this->legacy.IO_ADDR_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int au1300_nand_device_ready(struct nand_chip *this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct mtd_partition db1300_nand_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "NAND FS 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .size = 8 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = "NAND FS 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .size = MTDPART_SIZ_FULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct platform_nand_data db1300_nand_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .chip_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .partitions = db1300_nand_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .chip_delay = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .dev_ready = au1300_nand_device_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .cmd_ctrl = au1300_nand_cmd_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct resource db1300_nand_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .start = DB1300_NAND_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .end = DB1300_NAND_PHYS_ADDR + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct platform_device db1300_nand_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_resources = ARRAY_SIZE(db1300_nand_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .resource = db1300_nand_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .platform_data = &db1300_nand_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct resource db1300_eth_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .start = DB1300_ETH_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .end = DB1300_ETH_PHYS_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .start = DB1300_ETH_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .end = DB1300_ETH_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct smsc911x_platform_config db1300_eth_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .phy_interface = PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .flags = SMSC911X_USE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct platform_device db1300_eth_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .num_resources = ARRAY_SIZE(db1300_eth_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .resource = db1300_eth_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .platform_data = &db1300_eth_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct resource au1300_psc1_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .start = AU1300_PSC1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .start = AU1300_PSC1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .end = AU1300_PSC1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .start = AU1300_DSCR_CMD0_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .end = AU1300_DSCR_CMD0_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .start = AU1300_DSCR_CMD0_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .end = AU1300_DSCR_CMD0_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct platform_device db1300_ac97_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "au1xpsc_ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .id = 1, /* PSC ID. match with AC97 codec ID! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .num_resources = ARRAY_SIZE(au1300_psc1_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .resource = au1300_psc1_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct resource au1300_psc2_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .start = AU1300_PSC2_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .start = AU1300_PSC2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .end = AU1300_PSC2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .start = AU1300_DSCR_CMD0_PSC2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .end = AU1300_DSCR_CMD0_PSC2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .start = AU1300_DSCR_CMD0_PSC2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .end = AU1300_DSCR_CMD0_PSC2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct platform_device db1300_i2s_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .name = "au1xpsc_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .id = 2, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .num_resources = ARRAY_SIZE(au1300_psc2_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .resource = au1300_psc2_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct resource au1300_psc3_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .start = AU1300_PSC3_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .start = AU1300_PSC3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .end = AU1300_PSC3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .start = AU1300_DSCR_CMD0_PSC3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .end = AU1300_DSCR_CMD0_PSC3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .start = AU1300_DSCR_CMD0_PSC3_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .end = AU1300_DSCR_CMD0_PSC3_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct platform_device db1300_i2c_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "au1xpsc_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .id = 0, /* bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .num_resources = ARRAY_SIZE(au1300_psc3_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .resource = au1300_psc3_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* proper key assignments when facing the LCD panel. For key assignments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * according to the schematics swap up with down and left with right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * I chose to use it to emulate the arrow keys of a keyboard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .code = KEY_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .gpio = AU1300_PIN_LCDPWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .debounce_interval = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .desc = "5waysw-down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .code = KEY_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .gpio = AU1300_PIN_PSC2SYNC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .debounce_interval = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .desc = "5waysw-up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .code = KEY_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .gpio = AU1300_PIN_WAKE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .debounce_interval = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .desc = "5waysw-right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .code = KEY_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .gpio = AU1300_PIN_WAKE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .debounce_interval = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .desc = "5waysw-left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .code = KEY_ENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .gpio = AU1300_PIN_WAKE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .debounce_interval = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .desc = "5waysw-push",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct gpio_keys_platform_data db1300_5waysw_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .buttons = db1300_5waysw_arrowkeys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .rep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "db1300-5wayswitch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct platform_device db1300_5waysw_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .name = "gpio-keys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .platform_data = &db1300_5waysw_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct pata_platform_info db1300_ide_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .ioport_shift = DB1300_IDE_REG_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct resource db1300_ide_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .start = DB1300_IDE_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .start = DB1300_IDE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .end = DB1300_IDE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct platform_device db1300_ide_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .platform_data = &db1300_ide_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "pata_platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .resource = db1300_ide_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .num_resources = ARRAY_SIZE(db1300_ide_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void (*mmc_cd)(struct mmc_host *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* link against CONFIG_MMC=m. We can only be called once MMC core has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * initialized the controller, so symbol_get() should always succeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mmc_cd = symbol_get(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mmc_cd(ptr, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) symbol_put(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msleep(100); /* debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (irq == DB1300_SD1_INSERT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) enable_irq(DB1300_SD1_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enable_irq(DB1300_SD1_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int db1300_mmc_card_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int db1300_mmc_card_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int db1300_mmc_cd_setup(void *mmc_host, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = request_threaded_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) db1300_mmc_cdfn, 0, "sd_insert", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = request_threaded_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) db1300_mmc_cdfn, 0, "sd_eject", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) free_irq(DB1300_SD1_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (db1300_mmc_card_inserted(mmc_host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enable_irq(DB1300_SD1_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) enable_irq(DB1300_SD1_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) free_irq(DB1300_SD1_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) free_irq(DB1300_SD1_EJECT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void db1300_mmcled_set(struct led_classdev *led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum led_brightness brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (brightness != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct led_classdev db1300_mmc_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .brightness_set = db1300_mmcled_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct au1xmmc_platform_data db1300_sd1_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .cd_setup = db1300_mmc_cd_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .card_inserted = db1300_mmc_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .card_readonly = db1300_mmc_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .led = &db1300_mmc_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct resource au1300_sd1_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .start = AU1300_SD1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .end = AU1300_SD1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .start = AU1300_SD1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .end = AU1300_SD1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .start = AU1300_DSCR_CMD0_SDMS_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .end = AU1300_DSCR_CMD0_SDMS_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .start = AU1300_DSCR_CMD0_SDMS_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .end = AU1300_DSCR_CMD0_SDMS_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct platform_device db1300_sd1_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .platform_data = &db1300_sd1_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .resource = au1300_sd1_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .num_resources = ARRAY_SIZE(au1300_sd1_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int db1300_movinand_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0; /* disable for now, it doesn't work yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int db1300_movinand_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void db1300_movinand_led_set(struct led_classdev *led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) enum led_brightness brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (brightness != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct led_classdev db1300_movinand_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .brightness_set = db1300_movinand_led_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct au1xmmc_platform_data db1300_sd0_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .card_inserted = db1300_movinand_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .card_readonly = db1300_movinand_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .led = &db1300_movinand_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .mask_host_caps = MMC_CAP_NEEDS_POLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct resource au1300_sd0_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .start = AU1100_SD0_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .end = AU1100_SD0_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .start = AU1300_SD0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .end = AU1300_SD0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .start = AU1300_DSCR_CMD0_SDMS_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .end = AU1300_DSCR_CMD0_SDMS_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .start = AU1300_DSCR_CMD0_SDMS_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .end = AU1300_DSCR_CMD0_SDMS_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct platform_device db1300_sd0_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .platform_data = &db1300_sd0_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .resource = au1300_sd0_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_resources = ARRAY_SIZE(au1300_sd0_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct platform_device db1300_wm9715_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .name = "wm9712-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static struct platform_device db1300_ac97dma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "au1xpsc-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .id = 1, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static struct platform_device db1300_i2sdma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .name = "au1xpsc-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .id = 2, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct platform_device db1300_sndac97_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = "db1300-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static struct platform_device db1300_sndi2s_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .name = "db1300-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int db1300fb_panel_index(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 9; /* DB1300_800x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int db1300fb_panel_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) BCSR_BOARD_LCDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int db1300fb_panel_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct au1200fb_platdata db1300fb_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .panel_index = db1300fb_panel_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .panel_init = db1300fb_panel_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .panel_shutdown = db1300fb_panel_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct resource au1300_lcd_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .start = AU1200_LCD_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .start = AU1300_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .end = AU1300_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static struct platform_device db1300_lcd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "au1200-lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .dma_mask = &au1300_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .platform_data = &db1300fb_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .num_resources = ARRAY_SIZE(au1300_lcd_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .resource = au1300_lcd_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #if IS_ENABLED(CONFIG_TOUCHSCREEN_WM97XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) enable_irq(DB1300_AC97_PEN_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) disable_irq_nosync(DB1300_AC97_PEN_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct wm97xx_mach_ops db1300_wm97xx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .irq_enable = db1300_wm97xx_irqen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .irq_gpio = WM97XX_GPIO_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int db1300_wm97xx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct wm97xx *wm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* external pendown indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) WM97XX_GPIO_WAKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* internal "virtual" pendown gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) WM97XX_GPIO_NOWAKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) wm->pen_irq = DB1300_AC97_PEN_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int db1300_wm97xx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct platform_driver db1300_wm97xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .driver.name = "wm97xx-touch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .driver.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .probe = db1300_wm97xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static struct platform_device *db1300_dev[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) &db1300_eth_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) &db1300_i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) &db1300_5waysw_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) &db1300_nand_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) &db1300_ide_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) &db1300_sd0_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &db1300_sd1_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &db1300_lcd_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) &db1300_ac97_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) &db1300_i2s_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) &db1300_wm9715_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) &db1300_ac97dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &db1300_i2sdma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) &db1300_sndac97_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &db1300_sndi2s_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int __init db1300_dev_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int swapped, cpldirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* setup CPLD IRQ muxer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* insert/eject IRQs: one always triggers so don't enable them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * when doing request_irq() on them. DB1200 has this bug too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * setup board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) i2c_register_board_info(0, db1300_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ARRAY_SIZE(db1300_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (platform_driver_register(&db1300_wm97xx_driver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pr_warn("DB1300: failed to init touch pen irq support!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Audio PSC clock is supplied by codecs (PSC1, 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) __raw_writel(PSC_SEL_CLK_SERCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __raw_writel(PSC_SEL_CLK_SERCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* I2C driver wants 50MHz, get as close as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) c = clk_get(NULL, "psc3_intclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk_set_rate(c, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) clk_prepare_enable(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clk_put(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __raw_writel(PSC_SEL_CLK_INTCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* enable power to USB ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* although it is socket #0, it uses the CPLD bits which previous boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * have used for socket #1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) db1x_register_pcmcia_socket(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) AU1000_PCMCIA_ATTR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) AU1000_PCMCIA_MEM_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) AU1000_PCMCIA_IO_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) db1x_register_norflash(64 << 20, 2, swapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int __init db1300_board_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned short whoami;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) bcsr_init(DB1300_BCSR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) whoami = bcsr_read(BCSR_WHOAMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) db1300_gpio_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "BoardID %d CPLD Rev %d DaughtercardID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) BCSR_WHOAMI_DCID(whoami));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* enable UARTs, YAMON only enables #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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