^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DBAu1200/PBAu1200 board platform device registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2011 Manuel Lauss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-au1x00/au1100_mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach-au1x00/au1xxx_dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach-au1x00/au1xxx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-au1x00/au1200fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach-au1x00/au1550_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach-db1x00/bcsr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BCSR_INT_IDE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCSR_INT_ETH 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCSR_INT_PC0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BCSR_INT_PC0STSCHG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCSR_INT_PC1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BCSR_INT_PC1STSCHG 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCSR_INT_DC 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCSR_INT_FLASHBUSY 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BCSR_INT_PC0INSERT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BCSR_INT_PC0EJECT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BCSR_INT_PC1INSERT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BCSR_INT_PC1EJECT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BCSR_INT_SD0INSERT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BCSR_INT_SD0EJECT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BCSR_INT_SD1INSERT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BCSR_INT_SD1EJECT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DB1200_IDE_PHYS_ADDR 0x18800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DB1200_IDE_REG_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DB1200_ETH_PHYS_ADDR 0x19000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DB1200_NAND_PHYS_ADDR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PB1200_IDE_PHYS_ADDR 0x0C800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PB1200_ETH_PHYS_ADDR 0x0D000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PB1200_NAND_PHYS_ADDR 0x1C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DB1200_INT_END (DB1200_INT_BEGIN + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *get_system_type(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int __init db1200_detect_board(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int bid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* try the DB1200 first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bcsr_init(DB1200_BCSR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned short t = bcsr_read(BCSR_HEXLEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bcsr_write(BCSR_HEXLEDS, ~t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (bcsr_read(BCSR_HEXLEDS) != t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bcsr_write(BCSR_HEXLEDS, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* okay, try the PB1200 then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bcsr_init(PB1200_BCSR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (bid == BCSR_WHOAMI_PB1200_DDR2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned short t = bcsr_read(BCSR_HEXLEDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bcsr_write(BCSR_HEXLEDS, ~t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (bcsr_read(BCSR_HEXLEDS) != t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bcsr_write(BCSR_HEXLEDS, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 1; /* it's neither */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int __init db1200_board_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned short whoami;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (db1200_detect_board())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) whoami = bcsr_read(BCSR_WHOAMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (BCSR_WHOAMI_BOARD(whoami)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case BCSR_WHOAMI_PB1200_DDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case BCSR_WHOAMI_PB1200_DDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case BCSR_WHOAMI_DB1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) " Board-ID %d Daughtercard ID %d\n", get_system_type(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u64 au1200_all_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct mtd_partition db1200_spiflash_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "spi_flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct flash_platform_data db1200_spiflash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "s25fl001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .parts = db1200_spiflash_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .type = "m25p10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct spi_board_info db1200_spi_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* TI TMP121AIDBVR temp sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .modalias = "tmp121",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .max_speed_hz = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Spansion S25FL001D0FMA SPI flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .modalias = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .max_speed_hz = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .platform_data = &db1200_spiflash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct i2c_board_info db1200_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ioaddr &= 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ctrl & NAND_CLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ioaddr += MEM_STNAND_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else if (ctrl & NAND_ALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ioaddr += MEM_STNAND_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* assume we want to r/w real data by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ioaddr += MEM_STNAND_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (cmd != NAND_CMD_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __raw_writeb(cmd, this->legacy.IO_ADDR_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int au1200_nand_device_ready(struct nand_chip *this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct mtd_partition db1200_nand_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "NAND FS 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .size = 8 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "NAND FS 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .size = MTDPART_SIZ_FULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct platform_nand_data db1200_nand_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .chip_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .partitions = db1200_nand_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .chip_delay = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .dev_ready = au1200_nand_device_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .cmd_ctrl = au1200_nand_cmd_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct resource db1200_nand_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .start = DB1200_NAND_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .end = DB1200_NAND_PHYS_ADDR + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct platform_device db1200_nand_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .num_resources = ARRAY_SIZE(db1200_nand_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .resource = db1200_nand_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .platform_data = &db1200_nand_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct smc91x_platdata db1200_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .leda = RPC_LED_100_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ledb = RPC_LED_TX_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct resource db1200_eth_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .start = DB1200_ETH_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .end = DB1200_ETH_PHYS_ADDR + 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .start = DB1200_ETH_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .end = DB1200_ETH_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct platform_device db1200_eth_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .platform_data = &db1200_eth_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .num_resources = ARRAY_SIZE(db1200_eth_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .resource = db1200_eth_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct pata_platform_info db1200_ide_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .ioport_shift = DB1200_IDE_REG_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static struct resource db1200_ide_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .start = DB1200_IDE_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .start = DB1200_IDE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .end = DB1200_IDE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct platform_device db1200_ide_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "pata_platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .platform_data = &db1200_ide_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_resources = ARRAY_SIZE(db1200_ide_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .resource = db1200_ide_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* SD carddetects: they're supposed to be edge-triggered, but ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * is disabled and its counterpart enabled. The 200ms timeout is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * because the carddetect usually triggers twice, after debounce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void (*mmc_cd)(struct mmc_host *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* link against CONFIG_MMC=m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mmc_cd = symbol_get(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (mmc_cd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mmc_cd(ptr, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) symbol_put(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) msleep(100); /* debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (irq == DB1200_SD0_INSERT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enable_irq(DB1200_SD0_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) enable_irq(DB1200_SD0_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int db1200_mmc_cd_setup(void *mmc_host, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) free_irq(DB1200_SD0_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enable_irq(DB1200_SD0_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) enable_irq(DB1200_SD0_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) free_irq(DB1200_SD0_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) free_irq(DB1200_SD0_EJECT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void db1200_mmc_set_power(void *mmc_host, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msleep(400); /* stabilization time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int db1200_mmc_card_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int db1200_mmc_card_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void db1200_mmcled_set(struct led_classdev *led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) enum led_brightness brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (brightness != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct led_classdev db1200_mmc_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .brightness_set = db1200_mmcled_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void (*mmc_cd)(struct mmc_host *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* link against CONFIG_MMC=m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mmc_cd = symbol_get(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (mmc_cd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mmc_cd(ptr, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) symbol_put(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msleep(100); /* debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (irq == PB1200_SD1_INSERT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) enable_irq(PB1200_SD1_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) enable_irq(PB1200_SD1_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) free_irq(PB1200_SD1_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) enable_irq(PB1200_SD1_EJECT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) enable_irq(PB1200_SD1_INSERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) free_irq(PB1200_SD1_INSERT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) free_irq(PB1200_SD1_EJECT_INT, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void pb1200_mmc1led_set(struct led_classdev *led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) enum led_brightness brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (brightness != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct led_classdev pb1200_mmc1_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .brightness_set = pb1200_mmc1led_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void pb1200_mmc1_set_power(void *mmc_host, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msleep(400); /* stabilization time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int pb1200_mmc1_card_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int pb1200_mmc1_card_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .cd_setup = db1200_mmc_cd_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .set_power = db1200_mmc_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .card_inserted = db1200_mmc_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .card_readonly = db1200_mmc_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .led = &db1200_mmc_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .cd_setup = pb1200_mmc1_cd_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .set_power = pb1200_mmc1_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .card_inserted = pb1200_mmc1_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .card_readonly = pb1200_mmc1_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .led = &pb1200_mmc1_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct resource au1200_mmc0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .start = AU1100_SD0_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .end = AU1100_SD0_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .start = AU1200_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .end = AU1200_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .start = AU1200_DSCR_CMD0_SDMS_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .end = AU1200_DSCR_CMD0_SDMS_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .start = AU1200_DSCR_CMD0_SDMS_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .end = AU1200_DSCR_CMD0_SDMS_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct platform_device db1200_mmc0_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .platform_data = &db1200_mmc_platdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .resource = au1200_mmc0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct resource au1200_mmc1_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .start = AU1100_SD1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .end = AU1100_SD1_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .start = AU1200_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .end = AU1200_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .start = AU1200_DSCR_CMD0_SDMS_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .end = AU1200_DSCR_CMD0_SDMS_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .start = AU1200_DSCR_CMD0_SDMS_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .end = AU1200_DSCR_CMD0_SDMS_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct platform_device pb1200_mmc1_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .platform_data = &db1200_mmc_platdata[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .num_resources = ARRAY_SIZE(au1200_mmc1_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .resource = au1200_mmc1_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int db1200fb_panel_index(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int db1200fb_panel_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Apply power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) BCSR_BOARD_LCDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int db1200fb_panel_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Remove power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BCSR_BOARD_LCDBL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct au1200fb_platdata db1200fb_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .panel_index = db1200fb_panel_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .panel_init = db1200fb_panel_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .panel_shutdown = db1200fb_panel_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct resource au1200_lcd_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .start = AU1200_LCD_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .start = AU1200_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .end = AU1200_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct platform_device au1200_lcd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "au1200-lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .platform_data = &db1200fb_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .num_resources = ARRAY_SIZE(au1200_lcd_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .resource = au1200_lcd_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /**********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct resource au1200_psc0_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .start = AU1550_PSC0_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .start = AU1200_PSC0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .end = AU1200_PSC0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .start = AU1200_DSCR_CMD0_PSC0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .end = AU1200_DSCR_CMD0_PSC0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .start = AU1200_DSCR_CMD0_PSC0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .end = AU1200_DSCR_CMD0_PSC0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct platform_device db1200_i2c_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .name = "au1xpsc_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .id = 0, /* bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .num_resources = ARRAY_SIZE(au1200_psc0_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .resource = au1200_psc0_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static struct au1550_spi_info db1200_spi_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .mainclk_hz = 50000000, /* PSC0 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .num_chipselect = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .activate_cs = db1200_spi_cs_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct platform_device db1200_spi_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .platform_data = &db1200_spi_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "au1550-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .id = 0, /* bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .num_resources = ARRAY_SIZE(au1200_psc0_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .resource = au1200_psc0_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static struct resource au1200_psc1_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .start = AU1550_PSC1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .start = AU1200_PSC1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .end = AU1200_PSC1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .start = AU1200_DSCR_CMD0_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .end = AU1200_DSCR_CMD0_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .start = AU1200_DSCR_CMD0_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .end = AU1200_DSCR_CMD0_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* AC97 or I2S device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct platform_device db1200_audio_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* name assigned later based on switch setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .id = 1, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .num_resources = ARRAY_SIZE(au1200_psc1_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .resource = au1200_psc1_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* DB1200 ASoC card device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct platform_device db1200_sound_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* name assigned later based on switch setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .id = 1, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .dma_mask = &au1200_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static struct platform_device db1200_stac_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "ac97-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .id = 1, /* on PSC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static struct platform_device db1200_audiodma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "au1xpsc-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .id = 1, /* PSC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct platform_device *db1200_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) NULL, /* PSC0, selected by S6.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) &db1200_ide_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) &db1200_mmc0_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) &au1200_lcd_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) &db1200_eth_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) &db1200_nand_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) &db1200_audiodma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) &db1200_audio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &db1200_stac_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) &db1200_sound_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static struct platform_device *pb1200_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) &pb1200_mmc1_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Some peripheral base addresses differ on the PB1200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int __init pb1200_res_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* CPLD Revs earlier than 4 cause problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) printk(KERN_ERR "WARNING!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) printk(KERN_ERR "WARNING!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) printk(KERN_ERR "the board updated to latest revisions.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) printk(KERN_ERR "This software will not work reliably\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) printk(KERN_ERR "WARNING!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) printk(KERN_ERR "WARNING!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int __init db1200_dev_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned long pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned short sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int swapped, bid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (bid == BCSR_WHOAMI_PB1200_DDR2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (pb1200_res_fixup())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* GPIO7 is low-level triggered CPLD cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* SMBus/SPI on PSC0, Audio on PSC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* get 50MHz for I2C driver on PSC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) c = clk_get(NULL, "psc0_intclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pfc = clk_round_rate(c, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pr_warn("DB1200: cant get I2C close to 50MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clk_set_rate(c, pfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) clk_prepare_enable(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) clk_put(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* insert/eject pairs: one of both is always screaming. To avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * issues they must not be automatically enabled when initially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) i2c_register_board_info(0, db1200_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ARRAY_SIZE(db1200_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) spi_register_board_info(db1200_spi_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ARRAY_SIZE(db1200_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * or S12 on the PB1200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * this pin is claimed by PSC0 (unused though, but pinmux doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * allow to free it without crippling the SPI interface).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * As a result, in SPI mode, OTG simply won't work (PSC0 uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * it as an input pin which is pulled high on the boards).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* switch off OTG VBUS supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) gpio_request(215, "otg-vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) gpio_direction_output(215, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) printk(KERN_INFO "%s device configuration:\n", get_system_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) sw = bcsr_read(BCSR_SWITCHES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (sw & BCSR_SWITCHES_DIP_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) db1200_devs[0] = &db1200_i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) printk(KERN_INFO " OTG port VBUS supply available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) db1200_devs[0] = &db1200_spi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pfc |= (1 << 17); /* PSC0 owns GPIO215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) printk(KERN_INFO " OTG port VBUS supply disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (sw == BCSR_SWITCHES_DIP_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) db1200_audio_dev.name = "au1xpsc_i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) db1200_sound_dev.name = "db1200-i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) db1200_audio_dev.name = "au1xpsc_ac97";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) db1200_sound_dev.name = "db1200-ac97";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) __raw_writel(PSC_SEL_CLK_SERCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) db1x_register_pcmcia_socket(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) AU1000_PCMCIA_ATTR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) AU1000_PCMCIA_MEM_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) AU1000_PCMCIA_IO_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) db1x_register_pcmcia_socket(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) db1x_register_norflash(64 << 20, 2, swapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) (bid == BCSR_WHOAMI_PB1200_DDR2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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