^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DBAu1000/1500/1100 PBAu1100/1500 board support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2000, 2008 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/ads7846.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-au1x00/gpio-au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-au1x00/au1000_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach-au1x00/au1100_mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-db1x00/bcsr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const char *get_system_type(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int __init db1000_board_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* initialize board register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bcsr_init(DB1000_BCSR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case BCSR_WHOAMI_DB1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case BCSR_WHOAMI_DB1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case BCSR_WHOAMI_DB1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case BCSR_WHOAMI_PB1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case BCSR_WHOAMI_PB1500R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case BCSR_WHOAMI_PB1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pr_info("AMD Alchemy %s Board\n", get_system_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if ((slot < 12) || (slot > 13) || pin == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (slot == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return (pin == 1) ? AU1500_PCI_INTA : 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (slot == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 1: return AU1500_PCI_INTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 2: return AU1500_PCI_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case 3: return AU1500_PCI_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 4: return AU1500_PCI_INTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct resource alchemy_pci_host_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .start = AU1500_PCI_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .end = AU1500_PCI_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct alchemy_pci_platdata db1500_pci_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .board_map_irq = db1500_map_pci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct platform_device db1500_pci_host_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .dev.platform_data = &db1500_pci_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "alchemy-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .resource = alchemy_pci_host_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int __init db1500_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return platform_device_register(&db1500_pci_host_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct resource au1100_lcd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .start = AU1100_LCD_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .start = AU1100_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .end = AU1100_LCD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct platform_device au1100_lcd_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "au1100-lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .dma_mask = &au1xxx_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .num_resources = ARRAY_SIZE(au1100_lcd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .resource = au1100_lcd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct resource alchemy_ac97c_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .start = AU1000_AC97_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .end = AU1000_AC97_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .start = DMA_ID_AC97C_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .end = DMA_ID_AC97C_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .start = DMA_ID_AC97C_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .end = DMA_ID_AC97C_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct platform_device alchemy_ac97c_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "alchemy-ac97c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .resource = alchemy_ac97c_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct platform_device alchemy_ac97c_dma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "alchemy-pcm-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct platform_device db1x00_codec_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "ac97-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct platform_device db1x00_audio_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "db1000-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .dma_mask = &au1xxx_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void (*mmc_cd)(struct mmc_host *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* link against CONFIG_MMC=m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mmc_cd = symbol_get(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mmc_cd(ptr, msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) symbol_put(mmc_detect_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int db1100_mmc_cd_setup(void *mmc_host, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq = AU1100_GPIO19_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = request_irq(irq, db1100_mmc_cd, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "sd0_cd", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) free_irq(irq, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int db1100_mmc1_cd_setup(void *mmc_host, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) irq = AU1100_GPIO20_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = request_irq(irq, db1100_mmc_cd, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "sd1_cd", mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) free_irq(irq, mmc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int db1100_mmc_card_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* testing suggests that this bit is inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int db1100_mmc_card_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return !alchemy_gpio_get_value(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void db1100_mmc_set_power(void *mmc_host, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bit = BCSR_BOARD_SD0PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bit = BCSR_BOARD_PB1100_SD0PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bcsr_mod(BCSR_BOARD, 0, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) msleep(400); /* stabilization time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bcsr_mod(BCSR_BOARD, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (b != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct led_classdev db1100_mmc_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .brightness_set = db1100_mmcled_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int db1100_mmc1_card_readonly(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int db1100_mmc1_card_inserted(void *mmc_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return !alchemy_gpio_get_value(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void db1100_mmc1_set_power(void *mmc_host, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bit = BCSR_BOARD_SD1PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bit = BCSR_BOARD_PB1100_SD1PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bcsr_mod(BCSR_BOARD, 0, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) msleep(400); /* stabilization time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bcsr_mod(BCSR_BOARD, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (b != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct led_classdev db1100_mmc1_led = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .brightness_set = db1100_mmc1led_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .cd_setup = db1100_mmc_cd_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .set_power = db1100_mmc_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .card_inserted = db1100_mmc_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .card_readonly = db1100_mmc_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .led = &db1100_mmc_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .cd_setup = db1100_mmc1_cd_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .set_power = db1100_mmc1_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .card_inserted = db1100_mmc1_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .card_readonly = db1100_mmc1_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .led = &db1100_mmc1_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct resource au1100_mmc0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .start = AU1100_SD0_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .end = AU1100_SD0_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .start = AU1100_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .end = AU1100_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .start = DMA_ID_SD0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .end = DMA_ID_SD0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .start = DMA_ID_SD0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .end = DMA_ID_SD0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_device db1100_mmc0_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .dma_mask = &au1xxx_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .platform_data = &db1100_mmc_platdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .resource = au1100_mmc0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct resource au1100_mmc1_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .start = AU1100_SD1_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .end = AU1100_SD1_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .start = AU1100_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .end = AU1100_SD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .start = DMA_ID_SD1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .end = DMA_ID_SD1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .start = DMA_ID_SD1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .end = DMA_ID_SD1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct platform_device db1100_mmc1_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "au1xxx-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .dma_mask = &au1xxx_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .platform_data = &db1100_mmc_platdata[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .num_resources = ARRAY_SIZE(au1100_mmc1_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .resource = au1100_mmc1_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct ads7846_platform_data db1100_touch_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .model = 7846,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .vref_mv = 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .gpio_pendown = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct spi_gpio_platform_data db1100_spictl_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_chipselect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct spi_board_info db1100_spi_info[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .modalias = "ads7846",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .max_speed_hz = 3250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .irq = AU1100_GPIO21_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .platform_data = &db1100_touch_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct platform_device db1100_spi_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .platform_data = &db1100_spictl_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .dma_mask = &au1xxx_all_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Alchemy GPIO 2 has its base at 200 so the GPIO lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct gpiod_lookup_table db1100_spi_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .dev_id = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPIO_LOOKUP("alchemy-gpio2", 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "sck", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GPIO_LOOKUP("alchemy-gpio2", 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "mosi", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GPIO_LOOKUP("alchemy-gpio2", 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "miso", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GPIO_LOOKUP("alchemy-gpio2", 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "cs", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct platform_device *db1x00_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &db1x00_codec_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &alchemy_ac97c_dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &alchemy_ac97c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &db1x00_audio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct platform_device *db1100_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &au1100_lcd_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &db1100_mmc0_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &db1100_mmc1_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int __init db1000_dev_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct clk *c, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (board == BCSR_WHOAMI_DB1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) c0 = AU1500_GPIO2_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) c1 = AU1500_GPIO5_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) d0 = 0; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) d1 = 3; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) s0 = AU1500_GPIO1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) s1 = AU1500_GPIO4_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else if (board == BCSR_WHOAMI_DB1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) c0 = AU1100_GPIO2_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) c1 = AU1100_GPIO5_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) d0 = 0; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) d1 = 3; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) s0 = AU1100_GPIO1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) s1 = AU1100_GPIO4_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio_request(19, "sd0_cd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpio_request(20, "sd1_cd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) gpio_direction_input(19); /* sd0 cd# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpio_direction_input(20); /* sd1 cd# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* spi_gpio on SSI0 pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pfc |= (1 << 0); /* SSI0 pins as GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spi_register_board_info(db1100_spi_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ARRAY_SIZE(db1100_spi_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* link LCD clock to AUXPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) p = clk_get(NULL, "auxpll_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) c = clk_get(NULL, "lcd_intclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!IS_ERR(c) && !IS_ERR(p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clk_set_parent(c, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk_set_rate(c, clk_get_rate(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!IS_ERR(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_put(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!IS_ERR(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) clk_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) gpiod_add_lookup_table(&db1100_spi_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) platform_device_register(&db1100_spi_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else if (board == BCSR_WHOAMI_DB1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) c0 = AU1000_GPIO2_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) c1 = AU1000_GPIO5_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) d0 = 0; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) d1 = 3; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) s0 = AU1000_GPIO1_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) s1 = AU1000_GPIO4_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else if ((board == BCSR_WHOAMI_PB1500) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (board == BCSR_WHOAMI_PB1500R2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) c0 = AU1500_GPIO203_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) d0 = 1; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) s0 = AU1500_GPIO202_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) twosocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) flashsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* RTC and daughtercard irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* EPSON S1D13806 0x1b000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * SRAM 1MB/2MB 0x1a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * DS1693 RTC 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else if (board == BCSR_WHOAMI_PB1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) c0 = AU1100_GPIO11_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) d0 = 9; /* GPIO number, NOT irq! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) s0 = AU1100_GPIO10_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) twosocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) flashsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* pendown, rtc, daughtercard irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* EPSON S1D13806 0x1b000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * SRAM 1MB/2MB 0x1a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * DiskOnChip 0x0d000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * DS1693 RTC 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0; /* unknown board, no further dev setup to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) db1x_register_pcmcia_socket(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) AU1000_PCMCIA_ATTR_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) AU1000_PCMCIA_MEM_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) AU1000_PCMCIA_IO_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) c0, d0, /*s0*/0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (twosocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) db1x_register_pcmcia_socket(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) c1, d1, /*s1*/0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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