^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Previous incarnations were:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copied and modified Carsten Langgaard's time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ########################################################################
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ########################################################################
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * databooks). Firmware/Board init code must enable the counters in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * counter control register, otherwise the CP0 counter clocksource/event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * will be installed instead (and use of 'wait' instruction is prohibited).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* 32kHz clock enabled and detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u64 au1x_counter1_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return alchemy_rdsys(AU1000_SYS_RTCREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct clocksource au1x_counter1_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "alchemy-counter1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .read = au1x_counter1_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .rating = 1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int au1x_rtcmatch2_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* wait for register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clock_event_device *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct clock_event_device au1x_rtcmatch2_clockdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "rtcmatch2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .rating = 1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .set_next_event = au1x_rtcmatch2_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .cpumask = cpu_possible_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int __init alchemy_time_init(unsigned int m2int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) au1x_rtcmatch2_clockdev.irq = m2int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * has been detected. If so install the rtcmatch2 clocksource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * otherwise don't bother. Note that both bits being set is by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * no means a definite guarantee that the counters actually work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * (the 32S bit seems to be stuck set to 1 once a single clock-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * edge is detected, hence the timeouts).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) goto cntr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * setup counter 1 (RTC) to tick at full speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) t = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) asm volatile ("nop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto cntr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) t = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) asm volatile ("nop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto cntr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) t = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) asm volatile ("nop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto cntr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* register counter1 clocksource and event device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clocksource_register_hz(&au1x_counter1_clocksource, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cd->shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cd->max_delta_ticks = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cd->min_delta_ns = clockevent_delta2ns(9, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cd->min_delta_ticks = 9; /* ~0.28ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &au1x_rtcmatch2_clockdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("Failed to register timer interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) printk(KERN_INFO "Alchemy clocksource installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cntr_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int alchemy_m2inttab[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) AU1000_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) AU1500_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) AU1100_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) AU1550_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) AU1200_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) AU1300_RTC_MATCH2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) t = alchemy_get_cputype();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (t == ALCHEMY_CPU_UNKNOWN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) alchemy_time_init(alchemy_m2inttab[t]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cpu_wait = NULL; /* wait doesn't work with r4k timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags