Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2002 Embedded Edge, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: dan@embeddededge.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Sleep helper for Au1xxx sleep mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/stackframe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	.extern __flush_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	.set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	.set noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* preparatory stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) .macro	SETUP_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	subu	sp, PT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	sw	$1, PT_R1(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	sw	$2, PT_R2(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	sw	$3, PT_R3(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	sw	$4, PT_R4(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	sw	$5, PT_R5(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	sw	$6, PT_R6(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	sw	$7, PT_R7(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	sw	$16, PT_R16(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	sw	$17, PT_R17(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	sw	$18, PT_R18(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	sw	$19, PT_R19(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	sw	$20, PT_R20(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	sw	$21, PT_R21(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	sw	$22, PT_R22(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	sw	$23, PT_R23(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	sw	$26, PT_R26(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	sw	$27, PT_R27(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	sw	$28, PT_R28(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	sw	$30, PT_R30(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	sw	$31, PT_R31(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mfc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	sw	k0, 0x20(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	mfc0	k0, CP0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	sw	k0, 0x1c(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mfc0	k0, CP0_PAGEMASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	sw	k0, 0x18(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mfc0	k0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	sw	k0, 0x14(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* flush caches to make sure context is in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	la	t1, __flush_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	lw	t0, 0(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	jalr	t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Now set up the scratch registers so the boot rom will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * return to this point upon wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * sys_scratch0 : SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * sys_scratch1 : RA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	lui	t3, 0xb190		/* sys_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	sw	sp, 0x0018(t3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	la	k0, alchemy_sleep_wakeup	/* resume path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	sw	k0, 0x001c(t3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) .macro	DO_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* put power supply and processor to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	sw	zero, 0x0078(t3)	/* sys_slppwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	sw	zero, 0x007c(t3)	/* sys_sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* sleep code for Au1000/Au1100/Au1500 memory controller type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) LEAF(alchemy_sleep_au1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	SETUP_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* cache following instructions, as memory gets put to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	la	t0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.set	arch=r4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	cache	0x14, 0(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	cache	0x14, 32(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	cache	0x14, 64(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	cache	0x14, 96(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.set	mips0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 1:	lui	a0, 0xb400		/* mem_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	sw	zero, 0x001c(a0)	/* Precharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	sw	zero, 0x0020(a0)	/* Auto Refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	sw	zero, 0x0030(a0)	/* Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DO_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) END(alchemy_sleep_au1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* sleep code for Au1550/Au1200 memory controller type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LEAF(alchemy_sleep_au1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	SETUP_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* cache following instructions, as memory gets put to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	la	t0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.set	arch=r4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	cache	0x14, 0(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	cache	0x14, 32(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	cache	0x14, 64(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	cache	0x14, 96(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.set	mips0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 1:	lui	a0, 0xb400		/* mem_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	sw	zero, 0x08c0(a0)	/* Precharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sw	zero, 0x08d0(a0)	/* Self Refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* wait for sdram to enter self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	lui	t0, 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 2:	lw	t1, 0x0850(a0)		/* mem_sdstat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	and	t2, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	beq	t2, zero, 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* disable SDRAM clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	lui	t0, 0xcfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ori	t0, t0, 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	lw	t1, 0x0840(a0)		/* mem_sdconfiga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	and	t1, t0, t1		/* clear CE[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	sw	t1, 0x0840(a0)		/* mem_sdconfiga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	DO_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) END(alchemy_sleep_au1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* sleepcode for Au1300 memory controller type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) LEAF(alchemy_sleep_au1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	SETUP_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* cache following instructions, as memory gets put to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	la	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	la	t1, 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	subu	t2, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.set	arch=r4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 1:	cache	0x14, 0(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	subu	t2, t2, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	bgez	t2, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 addu	t0, t0, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.set	mips0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 2:	lui	a0, 0xb400		/* mem_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* disable all ports in mem_sdportcfga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	sw	zero, 0x868(a0)		/* mem_sdportcfga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* disable ODT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	li	t0, 0x03010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	sw	t0, 0x08d8(a0)		/* mem_sdcmd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	sw	t0, 0x08dc(a0)		/* mem_sdcmd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* precharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	li	t0, 0x23000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	sw	t0, 0x08dc(a0)		/* mem_sdcmd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	sw	t0, 0x08d8(a0)		/* mem_sdcmd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* auto refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	sw	zero, 0x08c8(a0)	/* mem_sdautoref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* block access to the DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	lw	t0, 0x0848(a0)		/* mem_sdconfigb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	li	t1, (1 << 7 | 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	or	t0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	sw	t0, 0x0848(a0)		/* mem_sdconfigb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* issue the Self Refresh command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	li	t0, 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	sw	t0, 0x08dc(a0)		/* mem_sdcmd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	sw	t0, 0x08d8(a0)		/* mem_sdcmd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* wait for sdram to enter self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	lui	t0, 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 3:	lw	t1, 0x0850(a0)		/* mem_sdstat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	and	t2, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bne	t2, t0, 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* disable SDRAM clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	li	t0, ~(3<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	lw	t1, 0x0840(a0)		/* mem_sdconfiga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	and	t1, t1, t0		/* clear CE[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	sw	t1, 0x0840(a0)		/* mem_sdconfiga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	DO_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) END(alchemy_sleep_au1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* This is where we return upon wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * Reload all of the registers and return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) LEAF(alchemy_sleep_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	lw	k0, 0x20(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mtc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	lw	k0, 0x1c(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	mtc0	k0, CP0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	lw	k0, 0x18(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mtc0	k0, CP0_PAGEMASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	lw	k0, 0x14(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	mtc0	k0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* We need to catch the early Alchemy SOCs with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * the write-only Config[OD] bit and set it back to one...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	jal	au1x00_fixup_config_od
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	lw	$1, PT_R1(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	lw	$2, PT_R2(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	lw	$3, PT_R3(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	lw	$4, PT_R4(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	lw	$5, PT_R5(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	lw	$6, PT_R6(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	lw	$7, PT_R7(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	lw	$16, PT_R16(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	lw	$17, PT_R17(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	lw	$18, PT_R18(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	lw	$19, PT_R19(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	lw	$20, PT_R20(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	lw	$21, PT_R21(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	lw	$22, PT_R22(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	lw	$23, PT_R23(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	lw	$26, PT_R26(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	lw	$27, PT_R27(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	lw	$28, PT_R28(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	lw	$30, PT_R30(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	lw	$31, PT_R31(sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 addiu	sp, PT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) END(alchemy_sleep_wakeup)