^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Au1xx0 Power Management routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001, 2008 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some of the routines are right out of init/main.c, whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * copyrights apply here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/sysctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * We need to save/restore a bunch of core registers that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * either volatile or reset to some state across a processor sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * If reading a register doesn't provide a proper result for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * later restore, we have to provide a function for loading that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * register and save a copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * We only have to save/restore registers that aren't otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * done as part of a driver pm_* function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static unsigned int sleep_sys_clocks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned int sleep_sys_pinfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static unsigned int sleep_static_memctlr[4][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void save_core_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Clocks and PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* pin mux config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Save the static memory controller configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void restore_core_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* restore clock configuration. Writing CPUPLL last will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * stall a bit and stabilize other clocks (unless this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * one of those Au1000 with a write-only PLL, where we dont
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * have a valid value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!au1xxx_cpu_has_pll_wo())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Restore the static memory controller configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void au_sleep(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) save_core_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case ALCHEMY_CPU_AU1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case ALCHEMY_CPU_AU1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case ALCHEMY_CPU_AU1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) alchemy_sleep_au1000();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case ALCHEMY_CPU_AU1550:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case ALCHEMY_CPU_AU1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) alchemy_sleep_au1550();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case ALCHEMY_CPU_AU1300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) alchemy_sleep_au1300();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) restore_core_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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