^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIOLIB support for Alchemy chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Notes :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * This file must ONLY be built when CONFIG_GPIOLIB=y and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * au1000 SoC have only one GPIO block : GPIO1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Au1100, Au15x0, Au12x0 have a second one : GPIO2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Au1300 is totally different: 1 block with up to 128 GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach-au1x00/gpio-au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach-au1x00/gpio-au1300.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int gpio2_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int gpio1_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void gpio1_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int gpio1_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct gpio_chip alchemy_gpio_chip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .label = "alchemy-gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .direction_input = gpio1_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .direction_output = gpio1_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .get = gpio1_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .set = gpio1_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .to_irq = gpio1_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .base = ALCHEMY_GPIO1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .ngpio = ALCHEMY_GPIO1_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .label = "alchemy-gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .direction_input = gpio2_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .direction_output = gpio2_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .get = gpio2_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .set = gpio2_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .to_irq = gpio2_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .base = ALCHEMY_GPIO2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .ngpio = ALCHEMY_GPIO2_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct gpio_chip au1300_gpiochip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .label = "alchemy-gpic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .direction_input = alchemy_gpic_dir_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .direction_output = alchemy_gpic_dir_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .get = alchemy_gpic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .set = alchemy_gpic_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .to_irq = alchemy_gpic_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .base = AU1300_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ngpio = AU1300_GPIO_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int __init alchemy_gpiochip_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case ALCHEMY_CPU_AU1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret |= gpiochip_add_data(&alchemy_gpio_chip[1], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case ALCHEMY_CPU_AU1300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = gpiochip_add_data(&au1300_gpiochip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) arch_initcall(alchemy_gpiochip_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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