^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * A DMA channel allocator for Au1x00. API is modeled loosely off of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * linux/kernel/dma.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2000, 2008 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/mach-au1x00/au1000_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * A note on resource allocation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * All drivers needing DMA channels, should allocate and release them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * through the public routines `request_dma()' and `free_dma()'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * In order to avoid problems, all processes should allocate resources in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * the same sequence and release them in the reverse order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * When releasing them, first release the IRQ, then release the DMA. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * main reason for this order is that, if you are requesting the DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * done interrupt, you won't know the irq number until the DMA channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * returned from request_dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* DMA Channel register block spacing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA_CHANNEL_LEN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_SPINLOCK(au1000_dma_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {.dev_id = -1,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {.dev_id = -1,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EXPORT_SYMBOL(au1000_dma_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Device FIFO addresses and default DMA modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct dma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } dma_dev_table[DMA_NUM_DEV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 }, /* UART0_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR }, /* UART0_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0, 0 }, /* DMA_REQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0, 0 }, /* DMA_REQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 }, /* AC97 TX c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int length, int *eof, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) chan = get_dma_chan(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (chan != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) len += sprintf(buf + len, "%2d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) i, chan->dev_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (fpos >= len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *start = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *eof = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *start = buf + fpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) len -= fpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (len > length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *eof = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Device FIFO addresses and default DMA modes - 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void dump_au1000_dma_channel(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (dmanr >= NUM_AU1000_DMA_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) chan = &au1000_dma_table[dmanr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) printk(KERN_INFO " mode = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __raw_readl(chan->io + DMA_MODE_SET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) printk(KERN_INFO " addr = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) printk(KERN_INFO " start0 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __raw_readl(chan->io + DMA_BUFFER0_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) printk(KERN_INFO " start1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __raw_readl(chan->io + DMA_BUFFER1_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) printk(KERN_INFO " count0 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __raw_readl(chan->io + DMA_BUFFER0_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) printk(KERN_INFO " count1 = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __raw_readl(chan->io + DMA_BUFFER1_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Finds a free channel, and binds the requested device to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Returns the allocated channel number, or negative on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Requests the DMA done IRQ if irqhandler != NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int request_au1000_dma(int dev_id, const char *dev_str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) irq_handler_t irqhandler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void *irq_dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct dma_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (au1000_dma_table[i].dev_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (i == NUM_AU1000_DMA_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) chan = &au1000_dma_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (dev_id >= DMA_NUM_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_id -= DMA_NUM_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev = &dma_dev_table_bank2[dev_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev = &dma_dev_table[dev_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (irqhandler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chan->irq_dev = irq_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) chan->irq_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) chan->irq_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) chan->irq_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* fill it in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i * DMA_CHANNEL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) chan->dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) chan->dev_str = dev_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chan->fifo_addr = dev->fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) chan->mode = dev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* initialize the channel before returning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) init_dma(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXPORT_SYMBOL(request_au1000_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void free_au1000_dma(unsigned int dmanr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct dma_chan *chan = get_dma_chan(dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) disable_dma(dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (chan->irq_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) free_irq(chan->irq, chan->irq_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) chan->irq_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) chan->dev_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) EXPORT_SYMBOL(free_au1000_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int __init au1000_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int base, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case ALCHEMY_CPU_AU1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) base = AU1000_DMA_INT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case ALCHEMY_CPU_AU1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) base = AU1500_DMA_INT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case ALCHEMY_CPU_AU1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) base = AU1100_DMA_INT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) au1000_dma_table[i].irq = base + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) printk(KERN_INFO "Alchemy DMA initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) arch_initcall(au1000_dma_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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