^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The Descriptor Based DMA channel manager that first appeared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * on the Au1550. I started with dma.c, but I think all that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * left is this initial comment :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2004 Embedded Edge, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * dan@embeddededge.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/mach-au1x00/au1xxx_dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The Descriptor Based DMA supports up to 16 channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * There are 32 devices defined. We keep an internal structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * of devices using these channels, along with additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * We allocate the descriptors and allow access to them through various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * functions. The drivers allocate the data buffers and assign them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * to the descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* I couldn't find a macro that did this... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static dbdma_global_t *dbdma_gptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int dbdma_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static dbdev_tab_t *dbdev_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* UARTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* EXT DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* USB DEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* PSCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* MAC 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* MAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 32 predefined plus 32 custom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DBDEV_TAB_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static dbdev_tab_t *find_dbdev_id(u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dbdev_tab_t *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) p = &dbdev_tab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (p->dev_id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dbdev_tab_t *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static u16 new_id = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) p = find_dbdev_id(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (NULL != p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) memcpy(p, dev, sizeof(dbdev_tab_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = p->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) new_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) p->dev_id, p->dev_flags, p->dev_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EXPORT_SYMBOL(au1xxx_ddma_add_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void au1xxx_ddma_del_device(u32 devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dbdev_tab_t *p = find_dbdev_id(devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (p != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) memset(p, 0, sizeof(dbdev_tab_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) p->dev_id = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXPORT_SYMBOL(au1xxx_ddma_del_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Allocate a channel and return a non-zero descriptor if successful. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void (*callback)(int, void *), void *callparam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 used, chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 dcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dbdev_tab_t *stp, *dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * We do the initialization on the first channel allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * We have to wait because of the interrupt handler initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * which can't be done successfully during board set up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!dbdma_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) stp = find_dbdev_id(srcid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (stp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dtp = find_dbdev_id(destid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (dtp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Check to see if we can get both channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Got source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) stp->dev_flags |= DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Got destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dtp->dev_flags |= DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Can't get dest. Release src. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) stp->dev_flags &= ~DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Let's see if we can allocate a channel for it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ctp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; i < NUM_DBDMA_CHANS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (chan_tab_ptr[i] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * If kmalloc fails, it is caught below same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * as a channel not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) chan_tab_ptr[i] = ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ctp != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) memset(ctp, 0, sizeof(chan_tab_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctp->chan_index = chan = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dcp += (0x0100 * chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cp = (au1x_dma_chan_t *)dcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctp->chan_src = stp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ctp->chan_dest = dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ctp->chan_callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ctp->chan_callparam = callparam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Initialize channel configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (stp->dev_intlevel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) i |= DDMA_CFG_SED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (stp->dev_intpolarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) i |= DDMA_CFG_SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (dtp->dev_intlevel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) i |= DDMA_CFG_DED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (dtp->dev_intpolarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) i |= DDMA_CFG_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (dtp->dev_flags & DEV_FLAGS_SYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) i |= DDMA_CFG_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) cp->ddma_cfg = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Return a non-zero value that can be used to find the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * information in subsequent operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return (u32)(&chan_tab_ptr[chan]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Release devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) stp->dev_flags &= ~DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dtp->dev_flags &= ~DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Set the device width if source or destination is a FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Should be 8, 16, or 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dbdev_tab_t *stp, *dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) stp = ctp->chan_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dtp = ctp->chan_dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rv = stp->dev_devwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) stp->dev_devwidth = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rv = dtp->dev_devwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dtp->dev_devwidth = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Allocate a descriptor ring, initializing as much as possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 desc_base, srcid, destid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 cmd0, cmd1, src1, dest1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 src0, dest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dbdev_tab_t *stp, *dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * I guess we could check this to be within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * range of the table......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) stp = ctp->chan_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dtp = ctp->chan_dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * The descriptors must be 32-byte aligned. There is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * possibility the allocation will give us such an address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * and if we try that first we are likely to not waste larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * slabs of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) desc_base = (u32)kmalloc_array(entries, sizeof(au1x_ddma_desc_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GFP_KERNEL|GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (desc_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (desc_base & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Lost....do it again, allocate extra, and round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * the address base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) kfree((const void *)desc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i = entries * sizeof(au1x_ddma_desc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) i += (sizeof(au1x_ddma_desc_t) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (desc_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ctp->cdb_membase = desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ctp->cdb_membase = desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dp = (au1x_ddma_desc_t *)desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Keep track of the base descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ctp->chan_desc_base = dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Initialize the rings with as much information as we know. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) srcid = stp->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) destid = dtp->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cmd0 = cmd1 = src1 = dest1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) src0 = dest0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cmd0 |= DSCR_CMD0_SID(srcid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cmd0 |= DSCR_CMD0_DID(destid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Is it mem to mem transfer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cmd0 |= DSCR_CMD0_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (stp->dev_devwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) switch (dtp->dev_devwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * If the device is marked as an in/out FIFO, ensure it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * set non-coherent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (stp->dev_flags & DEV_FLAGS_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (dtp->dev_flags & DEV_FLAGS_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Set up source1. For now, assume no stride and increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * A channel attribute update can change this later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) switch (stp->dev_tsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* If source input is FIFO, set static address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (stp->dev_flags & DEV_FLAGS_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (stp->dev_physaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) src0 = stp->dev_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Set up dest1. For now, assume no stride and increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * A channel attribute update can change this later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (dtp->dev_tsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* If destination output is FIFO, set static address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (dtp->dev_flags & DEV_FLAGS_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (dtp->dev_physaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dest0 = dtp->dev_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "source1:%x dest0:%x dest1:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) src1, dest0, dest1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dp->dscr_cmd0 = cmd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dp->dscr_cmd1 = cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dp->dscr_source0 = src0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dp->dscr_source1 = src1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dp->dscr_dest0 = dest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dp->dscr_dest1 = dest1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dp->dscr_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dp->sw_context = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dp->sw_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Make last descrptor point to the first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dp--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return (u32)ctp->chan_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Put a source buffer into the DMA ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * This updates the source pointer and byte count. Normally used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * for memory to fifo transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * I guess we could check this to be within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * range of the table......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ctp = *(chan_tab_t **)chanid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * We should have multiple callers for a particular channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * an interrupt doesn't affect this pointer nor the descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * so no locking should be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dp = ctp->put_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * If the descriptor is valid, we are way ahead of the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * engine, so just return an error condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (dp->dscr_cmd0 & DSCR_CMD0_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Load up buffer address and byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dp->dscr_source0 = buf & ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dp->dscr_cmd1 = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Check flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (flags & DDMA_FLAGS_IE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dp->dscr_cmd0 |= DSCR_CMD0_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (flags & DDMA_FLAGS_NOIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * There is an errata on the Au1200/Au1550 parts that could result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * in "stale" data being DMA'ed. It has to do with the snoop logic on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * the cache eviction buffer. DMA_NONCOHERENT is on by default for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * these parts. If it is fixed in the future, these dma_cache_inv will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * just be nothing more than empty macros. See io.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dma_cache_wback_inv((unsigned long)buf, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ctp->chan_ptr->ddma_dbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Get next descriptor pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Return something non-zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) EXPORT_SYMBOL(au1xxx_dbdma_put_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Put a destination buffer into the DMA ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * This updates the destination pointer and byte count. Normally used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * to place an empty buffer into the ring for fifo to memory transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* I guess we could check this to be within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * range of the table......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* We should have multiple callers for a particular channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * an interrupt doesn't affect this pointer nor the descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * so no locking should be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dp = ctp->put_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* If the descriptor is valid, we are way ahead of the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * engine, so just return an error condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (dp->dscr_cmd0 & DSCR_CMD0_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Load up buffer address and byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Check flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (flags & DDMA_FLAGS_IE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dp->dscr_cmd0 |= DSCR_CMD0_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (flags & DDMA_FLAGS_NOIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dp->dscr_dest0 = buf & ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dp->dscr_cmd1 = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * There is an errata on the Au1200/Au1550 parts that could result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * "stale" data being DMA'ed. It has to do with the snoop logic on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * cache eviction buffer. DMA_NONCOHERENT is on by default for these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * parts. If it is fixed in the future, these dma_cache_inv will just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * be nothing more than empty macros. See io.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dma_cache_inv((unsigned long)buf, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ctp->chan_ptr->ddma_dbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Get next descriptor pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Return something non-zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Get a destination buffer into the DMA ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Normally used to get a full buffer from the ring during fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * to memory transfers. This does not set the valid bit, you will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * have to put another destination buffer to keep the DMA going.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * I guess we could check this to be within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * range of the table......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * We should have multiple callers for a particular channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * an interrupt doesn't affect this pointer nor the descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * so no locking should be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dp = ctp->get_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * If the descriptor is valid, we are way ahead of the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * engine, so just return an error condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (dp->dscr_cmd0 & DSCR_CMD0_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Return buffer address and byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *buf = (void *)(phys_to_virt(dp->dscr_dest0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *nbytes = dp->dscr_cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rv = dp->dscr_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Get next descriptor pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Return something non-zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) void au1xxx_dbdma_stop(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int halt_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cp = ctp->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) while (!(cp->ddma_stat & DDMA_STAT_H)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) halt_timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (halt_timeout > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) printk(KERN_WARNING "warning: DMA channel won't halt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* clear current desc valid and doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) EXPORT_SYMBOL(au1xxx_dbdma_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Start using the current descriptor pointer. If the DBDMA encounters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * a non-valid descriptor, it will stop. In this case, we can just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * continue by adding a buffer to the list and starting again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) void au1xxx_dbdma_start(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cp = ctp->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cp->ddma_dbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) EXPORT_SYMBOL(au1xxx_dbdma_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) void au1xxx_dbdma_reset(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) au1xxx_dbdma_stop(chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Run through the descriptors and reset the valid indicator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dp = ctp->chan_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dp->dscr_cmd0 &= ~DSCR_CMD0_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Reset our software status -- this is used to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * if a descriptor is in use by upper level software. Since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * posting can reset 'V' bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dp->sw_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) } while (dp != ctp->chan_desc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) EXPORT_SYMBOL(au1xxx_dbdma_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 au1xxx_get_dma_residue(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) cp = ctp->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* This is only valid if the channel is stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) rv = cp->ddma_bytecnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) void au1xxx_dbdma_chan_free(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dbdev_tab_t *stp, *dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) stp = ctp->chan_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dtp = ctp->chan_dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) au1xxx_dbdma_stop(chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) kfree((void *)ctp->cdb_membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) stp->dev_flags &= ~DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dtp->dev_flags &= ~DEV_FLAGS_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) chan_tab_ptr[ctp->chan_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) kfree(ctp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 chan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) intstat = dbdma_gptr->ddma_intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) chan_index = __ffs(intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ctp = chan_tab_ptr[chan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cp = ctp->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dp = ctp->cur_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Reset interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) cp->ddma_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ctp->chan_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ctp->chan_callback(irq, ctp->chan_callparam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return IRQ_RETVAL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) void au1xxx_dbdma_dump(u32 chanid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dbdev_tab_t *stp, *dtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) au1x_dma_chan_t *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) stp = ctp->chan_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dtp = ctp->chan_dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cp = ctp->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dtp - dbdev_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) cp->ddma_bytecnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Run through the descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dp = ctp->chan_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dp->dscr_source0, dp->dscr_source1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dp->dscr_dest0, dp->dscr_dest1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dp->dscr_stat, dp->dscr_nxtptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } while (dp != ctp->chan_desc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Put a descriptor into the DMA ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * This updates the source/destination pointers and byte count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) chan_tab_t *ctp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) au1x_ddma_desc_t *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 nbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * I guess we could check this to be within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * range of the table......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ctp = *((chan_tab_t **)chanid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * We should have multiple callers for a particular channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * an interrupt doesn't affect this pointer nor the descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * so no locking should be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dp = ctp->put_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * If the descriptor is valid, we are way ahead of the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * engine, so just return an error condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (dp->dscr_cmd0 & DSCR_CMD0_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Load up buffer addresses and byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dp->dscr_dest0 = dscr->dscr_dest0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dp->dscr_source0 = dscr->dscr_source0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dp->dscr_dest1 = dscr->dscr_dest1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dp->dscr_source1 = dscr->dscr_source1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dp->dscr_cmd1 = dscr->dscr_cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) nbytes = dscr->dscr_cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Allow the caller to specify if an interrupt is generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ctp->chan_ptr->ddma_dbell = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Get next descriptor pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Return something non-zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int alchemy_dbdma_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* save channel configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* halt channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) __raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) while (!(__raw_readl(addr + 0x14) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) addr += 0x100; /* next channel base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* disable channel interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) __raw_writel(0, addr + 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void alchemy_dbdma_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) __raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) __raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* restore channel configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) __raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) __raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) addr += 0x100; /* next channel base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static struct syscore_ops alchemy_dbdma_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .suspend = alchemy_dbdma_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .resume = alchemy_dbdma_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dbdev_tab = kcalloc(DBDEV_TAB_SIZE, sizeof(dbdev_tab_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!dbdev_tab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dbdev_tab[ret].dev_id = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dbdma_gptr->ddma_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dbdma_gptr->ddma_throttle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dbdma_gptr->ddma_inten = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dbdma_initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) register_syscore_ops(&alchemy_dbdma_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int __init alchemy_dbdma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case ALCHEMY_CPU_AU1550:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case ALCHEMY_CPU_AU1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case ALCHEMY_CPU_AU1300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) subsys_initcall(alchemy_dbdma_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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