^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MTX-1 platform devices registration (Au1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio_keys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <mtd/mtd-abi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-au1x00/gpio-au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-au1x00/au1xxx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return "MTX-1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void prom_putchar(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void mtx1_reset(char *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Jump to the reset vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void mtx1_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) " .set mips32 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) " wait \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) " .set mips0 \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __init board_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #if IS_ENABLED(CONFIG_USB_OHCI_HCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Enable USB power switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) alchemy_gpio_direction_output(204, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Initialize sys_pinfunc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) alchemy_wrsys(SYS_PF_NI2, AU1000_SYS_PINFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Initialize GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Enable LED and set it to green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) alchemy_gpio_direction_output(211, 1); /* green on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) alchemy_gpio_direction_output(212, 0); /* red off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pm_power_off = mtx1_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) _machine_halt = mtx1_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) _machine_restart = mtx1_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) printk(KERN_INFO "4G Systems MTX-1 Board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct gpio_keys_button mtx1_gpio_button[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .gpio = 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .code = BTN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .desc = "System button",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct gpio_keys_platform_data mtx1_buttons_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .buttons = mtx1_gpio_button,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct platform_device mtx1_button = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "gpio-keys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .platform_data = &mtx1_buttons_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct gpiod_lookup_table mtx1_wdt_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .dev_id = "mtx1-wdt.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Global number 215 is offset 15 on Alchemy GPIO 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GPIO_LOOKUP("alchemy-gpio2", 15, NULL, GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct platform_device mtx1_wdt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "mtx1-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct gpio_led default_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "mtx1:green",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .gpio = 211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "mtx1:red",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .gpio = 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct gpio_led_platform_data mtx1_led_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .num_leds = ARRAY_SIZE(default_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .leds = default_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct platform_device mtx1_gpio_leds = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "leds-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .platform_data = &mtx1_led_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct mtd_partition mtx1_mtd_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .size = 0x01C00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "yamon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .size = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .size = 0x002c0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "yamon env",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct physmap_flash_data mtx1_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .nr_parts = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .parts = mtx1_mtd_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct resource mtx1_mtd_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .start = 0x1e000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .end = 0x1fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct platform_device mtx1_mtd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .platform_data = &mtx1_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .resource = &mtx1_mtd_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct resource alchemy_pci_host_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .start = AU1500_PCI_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .end = AU1500_PCI_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int mtx1_pci_idsel(unsigned int devsel, int assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* This function is only necessary to support a proprietary Cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * adapter on the mtx-1 "singleboard" variant. It triggers a custom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (assert && devsel != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Suppress signal to Cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const char mtx1_irqtab[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return mtx1_irqtab[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct alchemy_pci_platdata mtx1_pci_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .board_map_irq = mtx1_map_pci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .board_pci_idsel = mtx1_pci_idsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PCI_CONFIG_CH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #if defined(__MIPSEB__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct platform_device mtx1_pci_host = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .dev.platform_data = &mtx1_pci_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "alchemy-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .resource = alchemy_pci_host_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct platform_device *mtx1_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &mtx1_pci_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &mtx1_gpio_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &mtx1_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) &mtx1_button,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) &mtx1_mtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .phy_search_highest_addr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .phy1_search_mac0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int __init mtx1_register_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc = gpio_request(mtx1_gpio_button[0].gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mtx1_gpio_button[0].desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) printk(KERN_INFO "mtx1: failed to request %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mtx1_gpio_button[0].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) gpio_direction_input(mtx1_gpio_button[0].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) gpiod_add_lookup_table(&mtx1_wdt_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) arch_initcall(mtx1_register_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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