Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * GPR board platform device registration (Au1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_data/i2c-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/mach-au1x00/gpio-au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) const char *get_system_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return "GPR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) void prom_putchar(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static void gpr_reset(char *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* switch System-LED to orange (red# and green# on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	alchemy_gpio_direction_output(4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	alchemy_gpio_direction_output(5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* trigger watchdog to reset board in 200ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	printk(KERN_EMERG "Triggering watchdog soft reset...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	raw_local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	alchemy_gpio_direction_output(1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	alchemy_gpio_set_value(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		cpu_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void gpr_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		cpu_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) void __init board_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	printk(KERN_INFO "Trapeze ITS GPR board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	pm_power_off = gpr_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	_machine_halt = gpr_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	_machine_restart = gpr_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* Enable UART1/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Take away Reset of UMTS-card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	alchemy_gpio_direction_output(215, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct resource gpr_wdt_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.start	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.end	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.name	= "gpr-adm6320-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.flags	= IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct platform_device gpr_wdt_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.name = "adm6320-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.num_resources = ARRAY_SIZE(gpr_wdt_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.resource = gpr_wdt_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * 0x00000000-0x00200000 : "kernel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * 0x00200000-0x00a00000 : "rootfs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * 0x01d00000-0x01f00000 : "config"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * 0x01c00000-0x01d00000 : "yamon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * 0x01d00000-0x01d40000 : "yamon env vars"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * 0x00000000-0x00a00000 : "kernel+rootfs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct mtd_partition gpr_mtd_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.name	= "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.size	= 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.name	= "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.size	= 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.name	= "config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.size	= 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.offset = 0x01d00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.name	= "yamon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.size	= 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.offset = 0x01c00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.name	= "yamon env vars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.size	= 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.name	= "kernel+rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.size	= 0x00a00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct physmap_flash_data gpr_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.width		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.nr_parts	= ARRAY_SIZE(gpr_mtd_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.parts		= gpr_mtd_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct resource gpr_mtd_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.start	= 0x1e000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.end	= 0x1fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct platform_device gpr_mtd_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name		= "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.platform_data	= &gpr_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.resource	= &gpr_mtd_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * LEDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct gpio_led gpr_gpio_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{	/* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.name			= "gpr:green",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.gpio			= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.active_low		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{	/* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.name			= "gpr:red",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.gpio			= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.active_low		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct gpio_led_platform_data gpr_led_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.num_leds = ARRAY_SIZE(gpr_gpio_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.leds = gpr_gpio_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct platform_device gpr_led_devices = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.name = "leds-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.platform_data = &gpr_led_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.dev_id = "i2c-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 * This should be on "GPIO2" which has base at 200 so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 * the global numbers 209 and 210 should correspond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 * local offsets 9 and 10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct i2c_gpio_platform_data gpr_i2c_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * The open drain mode is hardwired somewhere or an electrical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * property of the alchemy GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.sda_is_open_drain	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.scl_is_open_drain	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.udelay			= 2,		/* ~100 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.timeout		= HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct platform_device gpr_i2c_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.name			= "i2c-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.id			= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.dev.platform_data	= &gpr_i2c_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct i2c_board_info gpr_i2c_info[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		I2C_BOARD_INFO("lm83", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct resource alchemy_pci_host_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.start	= AU1500_PCI_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.end	= AU1500_PCI_PHYS_ADDR + 0xfff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if ((slot == 0) && (pin == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return AU1550_PCI_INTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	else if ((slot == 0) && (pin == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return AU1550_PCI_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct alchemy_pci_platdata gpr_pci_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.board_map_irq	= gpr_map_pci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.pci_cfg_set	= PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			  PCI_CONFIG_CH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #if defined(__MIPSEB__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			  0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct platform_device gpr_pci_host_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.dev.platform_data = &gpr_pci_pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.name		= "alchemy-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.num_resources	= ARRAY_SIZE(alchemy_pci_host_res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.resource	= alchemy_pci_host_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_device *gpr_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	&gpr_wdt_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	&gpr_mtd_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	&gpr_i2c_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	&gpr_led_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int __init gpr_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return platform_device_register(&gpr_pci_host_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) arch_initcall(gpr_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int __init gpr_dev_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) device_initcall(gpr_dev_init);