^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PCI support for Xilinx plbv46_pci soft-core which can be used on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx Virtex ML410 / ML510 boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Roderick Colenbrander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2009 Secret Lab Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * by Benjamin Herrenschmidt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XPLB_PCI_ADDR 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XPLB_PCI_DATA 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XPLB_PCI_BUS 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct of_device_id xilinx_pci_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { .compatible = "xlnx,plbv46-pci-1.03.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (dev->devfn || dev->bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) hose = pci_bus_to_host(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!of_match_node(xilinx_pci_match, hose->dn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Hide the PCI host BARs from the kernel as their content doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * fit well in the resource management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev->resource[i].start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev->resource[i].end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev->resource[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * xilinx_pci_exclude_device - Don't do config access for non-root bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * This is a hack. Config access to any bus other than bus 0 does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * currently work on the ML510 so we prevent it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (bus != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * xilinx_early_pci_scan - List pci config space for available devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * List pci devices in very early phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __init xilinx_early_pci_scan(struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 bus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 val, dev, func, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Currently we have only 2 device connected - up-to 32 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (dev = 0; dev < 2; dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* List only first function number - up-to 8 functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (func = 0; func < 1; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pr_info("%02x:%02x:%02x", bus, dev, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* read the first 64 standardized bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Up-to 192 bytes can be list of capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (offset = 0; offset < 64; offset += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) early_read_config_dword(hose, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PCI_DEVFN(dev, func), offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (offset == 0 && val == 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_cont("\nABSENT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!(offset % 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_cont("\n%04x: ", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pr_cont("%08x ", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void __init xilinx_early_pci_scan(struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * xilinx_pci_init - Find and register a Xilinx PCI host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __init xilinx_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *pci_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device_node *pci_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pci_node = of_find_matching_node(NULL, xilinx_pci_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!pci_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (of_address_to_resource(pci_node, 0, &r)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_err("xilinx-pci: cannot resolve base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hose = pcibios_alloc_controller(pci_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!hose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Setup config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) r.start + XPLB_PCI_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) INDIRECT_TYPE_SET_CFG_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* According to the xilinx plbv46_pci documentation the soft-core starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * a self-init when the bus master enable bit is set. Without this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * set the pci bus can't be scanned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Set the max latency timer to 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Set the max bus number to 255, and bus/subbus no's to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_reg = of_iomap(pci_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) WARN_ON(!pci_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) iounmap(pci_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Register the host bridge with the linux kernel! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_process_bridge_OF_ranges(hose, pci_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) INDIRECT_TYPE_SET_CFG_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_info("xilinx-pci: Registered PCI host bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xilinx_early_pci_scan(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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