^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Contains common pci routines for ALL ppc platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (based on pci_32.c and pci_64.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Port for PPC64 David Engebretsen, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Rework, based on alpha PCI code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Common pmac/prep/chrp pci routines. -- Cort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/shmem_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static DEFINE_SPINLOCK(hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) LIST_HEAD(hose_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* XXX kill that some day ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int global_phb_number; /* Global phb counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* ISA Memory physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) resource_size_t isa_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXPORT_SYMBOL(isa_io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int pci_bus_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct pci_controller *phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!phb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spin_lock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) phb->global_number = global_phb_number++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) list_add_tail(&phb->list_node, &hose_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spin_unlock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) phb->dn = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) phb->is_dynamic = mem_init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void pcibios_free_controller(struct pci_controller *phb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) list_del(&phb->list_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) spin_unlock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (phb->is_dynamic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) kfree(phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static resource_size_t pcibios_io_size(const struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return resource_size(&hose->io_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int pcibios_vaddr_is_ioport(void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_lock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) list_for_each_entry(hose, &hose_list, list_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) size = pcibios_io_size(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (address >= hose->io_base_virt &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) address < (hose->io_base_virt + size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_unlock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long pci_address_to_pio(phys_addr_t address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long ret = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) spin_lock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) list_for_each_entry(hose, &hose_list, list_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) size = pcibios_io_size(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (address >= hose->io_base_phys &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) address < (hose->io_base_phys + size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (unsigned long)hose->io_base_virt - _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = base + (address - hose->io_base_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_unlock(&hose_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXPORT_SYMBOL_GPL(pci_address_to_pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* This routine is meant to be used early during boot, when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * PCI bus numbers have not yet been assigned, and you need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * issue PCI config cycles to an OF device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * It could also be used to "fix" RTAS config cycles if you want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * to set pci_assign_all_buses to 1 and still use RTAS for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * config cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) while (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pci_controller *hose, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (hose->dn == node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) node = node->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void pcibios_set_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* No special bus mastering setup handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Platform support for /proc/bus/pci/X/Y mmap()s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pci_controller *hose = pci_bus_to_host(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) resource_size_t ioaddr = pci_resource_start(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EINVAL; /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Convert to an offset within this PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * This one is used by /dev/mem and fbdev who have no clue about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * PCI device, it tries to find the PCI device first and calls the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * above routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pgprot_t pci_phys_mem_access_prot(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pgprot_t prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct resource *found = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (page_is_ram(pfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) prot = pgprot_noncached(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for_each_pci_dev(pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct resource *rp = &pdev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int flags = rp->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Active and same type? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if ((flags & IORESOURCE_MEM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* In the range of this resource? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (offset < (rp->start & PAGE_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) offset > rp->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) found = rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (found->flags & IORESOURCE_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) prot = pgprot_noncached_wc(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (unsigned long long)offset, pgprot_val(prot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* This provides legacy IO read access on a bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct resource *rp = &hose->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Check if port can be supported by that bus. We only check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * the ranges of the PHB though, not the bus itself as the rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * for forwarding legacy cycles down bridges are not our problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * here. So if the host bridge supports it, we do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) offset = (unsigned long)hose->io_base_virt - _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) offset += port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!(rp->flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (offset < rp->start || (offset + size) > rp->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) addr = hose->io_base_virt + port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *((u8 *)val) = in_8(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (port & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *((u16 *)val) = in_le16(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (port & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *((u32 *)val) = in_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* This provides legacy IO write access on a bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct resource *rp = &hose->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Check if port can be supported by that bus. We only check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * the ranges of the PHB though, not the bus itself as the rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * for forwarding legacy cycles down bridges are not our problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * here. So if the host bridge supports it, we do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) offset = (unsigned long)hose->io_base_virt - _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) offset += port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!(rp->flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (offset < rp->start || (offset + size) > rp->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) addr = hose->io_base_virt + port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* WARNING: The generic code is idiotic. It gets passed a pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * to what can be a 1, 2 or 4 byte quantity and always reads that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * as a u32, which means that we have to correct the location of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * the data read within those 32 bits for size 1 and 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) out_8(addr, val >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (port & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) out_le16(addr, val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (port & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) out_le32(addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* This provides legacy IO or memory mmap access on a bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int pci_mmap_legacy_page_range(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enum pci_mmap_state mmap_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) resource_size_t offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) resource_size_t size = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct resource *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_domain_nr(bus), bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mmap_state == pci_mmap_mem ? "MEM" : "IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (unsigned long long)offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (unsigned long long)(offset + size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (mmap_state == pci_mmap_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Hack alert !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Because X is lame and can fail starting if it gets an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * trying to mmap legacy_mem (instead of just moving on without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * legacy memory access) we fake it here by giving it anonymous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * memory, effectively behaving just like /dev/zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((offset + size) > hose->isa_mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_debug("Process %s (pid:%d) mapped non-existing PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) current->comm, current->pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_debug("legacy memory for 0%04x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pci_domain_nr(bus), bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (vma->vm_flags & VM_SHARED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return shmem_zero_setup(vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) offset += hose->isa_mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long io_offset = (unsigned long)hose->io_base_virt -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long roffset = offset + io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rp = &hose->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!(rp->flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (roffset < rp->start || (roffset + size) > rp->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) offset += hose->io_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vma->vm_pgoff = offset >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) vma->vm_end - vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void pci_resource_to_user(const struct pci_dev *dev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct resource *rsrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) resource_size_t *start, resource_size_t *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (rsrc->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pcibios_resource_to_bus(dev->bus, ®ion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (struct resource *) rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *start = region.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *end = region.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* We pass a CPU physical address to userland for MMIO instead of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * BAR value because X is lame and expects to be able to use that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * to pass to /dev/mem!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * That means we may have 64-bit values where some apps only expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *start = rsrc->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *end = rsrc->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @hose: newly allocated pci_controller to be setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * @dev: device node of the host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * @primary: set if primary bus (32 bits only, soon to be deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * This function will parse the "ranges" property of a PCI host bridge device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * node and setup the resource mapping of a pci controller based on its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * content.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Life would be boring if it wasn't for a few issues that we have to deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * with here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * - We can only cope with one IO space range and up to 3 Memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * ranges. However, some machines (thanks Apple !) tend to split their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * space into lots of small contiguous ranges. So we have to coalesce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * - We can only cope with all memory ranges having the same offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * between CPU addresses and PCI addresses. Unfortunately, some bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * are setup for a large 1:1 mapping along with a small "window" which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * maps PCI address 0 to some arbitrary high address of the CPU space in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * order to give access to the ISA memory hole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * The way out of here that I've chosen for now is to always set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * offset based on the first resource found, then override it if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * have a different offset and the previous was set by an ISA hole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * - Some busses have IO space not starting at 0, which causes trouble with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * the way we do our IO resource renumbering. The code somewhat deals with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * it for 64 bits but I would expect problems on 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * - Some 32 bits platforms such as 4xx can have physical space larger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * 32 bits so we need to use 64 bits values for the parsing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void pci_process_bridge_OF_ranges(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct device_node *dev, int primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int memno = 0, isa_hole = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long long isa_mb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct of_pci_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct of_pci_range_parser parser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pr_info("PCI host bridge %pOF %s ranges:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev, primary ? "(primary)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Check for ranges property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (of_pci_range_parser_init(&parser, dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pr_debug("Parsing ranges property...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for_each_of_pci_range(&parser, &range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Read next ranges element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* If we failed translation or got a zero-sized region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * (some FW try to feed us with non sensical zero sized regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * such as power3 which look like some kind of attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * at exposing the VGA memory hole)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Act based on address space type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (range.flags & IORESOURCE_TYPE_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case IORESOURCE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) range.cpu_addr, range.cpu_addr + range.size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) range.pci_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* We support only one IO range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (hose->pci_io_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_info(" \\--> Skipped (too many) !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* On 32 bits, limit I/O space to 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (range.size > 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) range.size = 0x01000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* 32 bits needs to map IOs here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hose->io_base_virt = ioremap(range.cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) range.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Expect trouble if pci_addr is not 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) isa_io_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) (unsigned long)hose->io_base_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* pci_io_size and io_base_phys always represent IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * space starting at 0 so we factor in pci_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hose->pci_io_size = range.pci_addr + range.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hose->io_base_phys = range.cpu_addr - range.pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Build resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) res = &hose->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) range.cpu_addr = range.pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case IORESOURCE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) range.cpu_addr, range.cpu_addr + range.size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) range.pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (range.flags & IORESOURCE_PREFETCH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "Prefetch" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* We support only 3 memory ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (memno >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pr_info(" \\--> Skipped (too many) !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Handles ISA memory hole space here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (range.pci_addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) isa_mb = range.cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) isa_hole = memno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (primary || isa_mem_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) isa_mem_base = range.cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hose->isa_mem_phys = range.cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hose->isa_mem_size = range.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* We get the PCI/Mem offset from the first range or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * the, current one if the offset came from an ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * hole. If they don't match, bugger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (memno == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (isa_hole >= 0 && range.pci_addr != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hose->pci_mem_offset == isa_mb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hose->pci_mem_offset = range.cpu_addr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) range.pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else if (range.pci_addr != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hose->pci_mem_offset != range.cpu_addr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) range.pci_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pr_info(" \\--> Skipped (offset mismatch) !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Build resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) res = &hose->mem_resources[memno++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (res != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) res->name = dev->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) res->flags = range.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) res->start = range.cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) res->end = range.cpu_addr + range.size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) res->parent = res->child = res->sibling = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* If there's an ISA hole and the pci_mem_offset is -not- matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * the ISA hole offset, then we need to remove the ISA hole from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * the resource list for that brige
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int next = isa_hole + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (next < memno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) memmove(&hose->mem_resources[isa_hole],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &hose->mem_resources[next],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sizeof(struct resource) * (memno - next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hose->mem_resources[--memno].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Display the domain number in /proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int pci_proc_domain(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return pci_domain_nr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* This header fixup will do the resource fixup for all devices as they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * probed, but not for bridge ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void pcibios_fixup_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct pci_controller *hose = pci_bus_to_host(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!hose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pr_err("No host bridge for PCI dev %s !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct resource *res = dev->resource + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!res->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (res->start == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pci_name(dev), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (unsigned long long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (unsigned long long)res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) (unsigned int)res->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pr_debug("is unassigned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) res->end -= res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) res->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) res->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pci_name(dev), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) (unsigned long long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (unsigned long long)res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) (unsigned int)res->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int pcibios_add_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) EXPORT_SYMBOL(pcibios_add_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Reparent resource children of pr that conflict with res
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * under res, and make res replace those children.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int __init reparent_resources(struct resource *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct resource *p, **pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct resource **firstpp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (p->end < res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (res->end < p->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (p->start < res->start || p->end > res->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -1; /* not completely contained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (firstpp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) firstpp = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (firstpp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -1; /* didn't find any conflicting entries? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) res->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) res->child = *firstpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) res->sibling = *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *firstpp = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *pp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (p = res->child; p != NULL; p = p->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) p->parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) p->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) (unsigned long long)p->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (unsigned long long)p->end, res->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Handle resources of PCI devices. If the world were perfect, we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * just allocate all the resource regions and do nothing more. It isn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * On the other hand, we cannot just re-allocate all devices, as it would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * require us to know lots of host bridge internals. So we attempt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * keep as much of the original configuration as possible, but tweak it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * when it's found to be wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Known BIOS problems we have to work around:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * - I/O or memory regions not configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * - regions configured, but not enabled in the command register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * - bogus I/O addresses above 64K used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * - expansion ROMs left enabled (this may sound harmless, but given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * the fact the PCI specs explicitly allow address decoders to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * shared between expansion ROMs and other resource regions, it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * at least dangerous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Our solution:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * This gives us fixed barriers on where we can allocate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * (2) Allocate resources for all enabled devices. If there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * a collision, just mark the resource as unallocated. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * disable expansion ROMs during this step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * (3) Try to allocate resources for disabled devices. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * resources were assigned correctly, everything goes well,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * if they weren't, they won't disturb allocation of other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * (4) Assign new addresses to resources which were either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * not configured at all or misconfigured. If explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * requested by the user, configure expansion ROM address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void pcibios_allocate_bus_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct resource *res, *pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pci_domain_nr(bus), bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pci_bus_for_each_resource(bus, res, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!res || !res->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) || res->start > res->end || res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (bus->parent == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pr = (res->flags & IORESOURCE_IO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &ioport_resource : &iomem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Don't bother with non-root busses when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * re-assigning all resources. We clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * resource flags as if they were colliding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * and as such ensure proper re-allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pr = pci_find_parent_resource(bus->self, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (pr == res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* this happens when the generic PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * code (wrongly) decides that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * bridge is transparent -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) bus->self ? pci_name(bus->self) : "PHB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bus->number, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (unsigned long long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) (unsigned long long)res->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pr_debug("[0x%x], parent %p (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) (unsigned int)res->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr, (pr && pr->name) ? pr->name : "nil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (pr && !(pr->flags & IORESOURCE_UNSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct pci_dev *dev = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (request_resource(pr, res) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Must be a conflict with an existing entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * Move that entry (or entries) under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * bridge resource and try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (reparent_resources(pr, res) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pci_claim_bridge_resource(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) i + PCI_BRIDGE_RESOURCES) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_warn("PCI: Cannot allocate resource region ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) res->start = res->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) list_for_each_entry(b, &bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pcibios_allocate_bus_resources(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static inline void alloc_resource(struct pci_dev *dev, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct resource *pr, *r = &dev->resource[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pci_name(dev), idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) (unsigned long long)r->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (unsigned long long)r->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) (unsigned int)r->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pr = pci_find_parent_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!pr || (pr->flags & IORESOURCE_UNSET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) request_resource(pr, r) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pr_warn("PCI: Cannot allocate resource region %d ", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pr_cont("of device %s, will remap\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (unsigned long long)pr->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (unsigned long long)pr->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (unsigned int)pr->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* We'll assign a new address later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) r->end -= r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void __init pcibios_allocate_resources(int pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int idx, disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) r = &dev->resource[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (r->parent) /* Already allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!r->flags || (r->flags & IORESOURCE_UNSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) continue; /* Not assigned at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* We only allocate ROMs on pass 1 just in case they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * have been screwed up by firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (idx == PCI_ROM_RESOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (r->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) disabled = !(command & PCI_COMMAND_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) disabled = !(command & PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (pass == disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) alloc_resource(dev, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) r = &dev->resource[PCI_ROM_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (r->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Turn the ROM off, leave the resource region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * but keep it unregistered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pci_read_config_dword(dev, dev->rom_base_reg, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (reg & PCI_ROM_ADDRESS_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pr_debug("PCI: Switching off ROM of %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) r->flags &= ~IORESOURCE_ROM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pci_write_config_dword(dev, dev->rom_base_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) reg & ~PCI_ROM_ADDRESS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) resource_size_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct resource *res, *pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pr_debug("Reserving legacy ranges for domain %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pci_domain_nr(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Check for IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!(hose->io_resource.flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto no_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) offset = (unsigned long)hose->io_base_virt - _IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) res = kzalloc(sizeof(struct resource), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) BUG_ON(res == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) res->name = "Legacy IO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) res->start = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) res->end = (offset + 0xfff) & 0xfffffffful;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pr_debug("Candidate legacy IO: %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (request_resource(&hose->io_resource, res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pci_domain_nr(bus), bus->number, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) no_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Check for memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) offset = hose->pci_mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pres = &hose->mem_resources[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!(pres->flags & IORESOURCE_MEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pr_debug("hose mem res: %pR\n", pres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if ((pres->start - offset) <= 0xa0000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (pres->end - offset) >= 0xbffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (i >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) res = kzalloc(sizeof(struct resource), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) BUG_ON(res == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) res->name = "Legacy VGA memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) res->start = 0xa0000 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) res->end = 0xbffff + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pr_debug("Candidate VGA memory: %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (request_resource(pres, res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pci_domain_nr(bus), bus->number, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) void __init pcibios_resource_survey(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Allocate and assign resources. If we re-assign everything, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * we skip the allocate phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) list_for_each_entry(b, &pci_root_buses, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pcibios_allocate_bus_resources(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pcibios_allocate_resources(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pcibios_allocate_resources(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Before we start assigning unassigned resource, we try to reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * the low IO area and the VGA memory area if they intersect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * bus available resources to avoid allocating things on top of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) list_for_each_entry(b, &pci_root_buses, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pcibios_reserve_legacy_regions(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Now proceed to assigning things that were left unassigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pr_debug("PCI: Assigning unassigned resources...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pci_assign_unassigned_resources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static void pcibios_setup_phb_resources(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct list_head *resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unsigned long io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Hookup PHB IO resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) res = &hose->io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Fixup IO space offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) res->start = (res->start + io_offset) & 0xffffffffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) res->end = (res->end + io_offset) & 0xffffffffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!res->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pr_warn("PCI: I/O resource not set for host ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pr_cont("bridge %pOF (domain %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) hose->dn, hose->global_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Workaround for lack of IO resource only on 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) res->start = (unsigned long)hose->io_base_virt - isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) res->end = res->start + IO_SPACE_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pci_add_resource_offset(resources, res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (unsigned long long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) (unsigned long long)res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) (unsigned long)res->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Hookup PHB Memory resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) res = &hose->mem_resources[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!res->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pr_err("PCI: Memory resource 0 not set for ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pr_cont("host bridge %pOF (domain %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) hose->dn, hose->global_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* Workaround for lack of MEM resource only on 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) res->start = hose->pci_mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) res->end = (resource_size_t)-1LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pci_add_resource_offset(resources, res, hose->pci_mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) i, (unsigned long long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (unsigned long long)res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (unsigned long)res->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pr_debug("PCI: PHB MEM offset = %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) (unsigned long long)hose->pci_mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pr_debug("PCI: PHB IO offset = %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) (unsigned long)hose->io_base_virt - _IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static void pcibios_scan_phb(struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct device_node *node = hose->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pr_debug("PCI: Scanning PHB %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pcibios_setup_phb_resources(hose, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) bus = pci_scan_root_bus(hose->parent, hose->first_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) hose->ops, hose, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (bus == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pr_err("Failed to create bus for PCI domain %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) hose->global_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pci_free_resource_list(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) bus->busn_res.start = hose->first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) hose->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) hose->last_busno = bus->busn_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct pci_controller *hose, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int next_busno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pr_info("PCI: Probing PCI hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Scan all of the recorded PCI controllers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) hose->last_busno = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pcibios_scan_phb(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (next_busno <= hose->last_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) next_busno = hose->last_busno + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pci_bus_count = next_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Call common code to handle resource allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pcibios_resource_survey();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (hose->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pci_bus_add_devices(hose->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) subsys_initcall(pcibios_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static struct pci_controller *pci_bus_to_hose(int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct pci_controller *hose, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (bus >= hose->first_busno && bus <= hose->last_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Provide information on locations of various I/O regions in physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * memory. Do this on a per-card basis so that we choose the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * root bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Note that the returned IO or memory base is a physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) long result = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) hose = pci_bus_to_hose(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (!hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) case IOBASE_BRIDGE_NUMBER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return (long)hose->first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case IOBASE_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return (long)hose->pci_mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case IOBASE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return (long)hose->io_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case IOBASE_ISA_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return (long)isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) case IOBASE_ISA_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return (long)isa_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Null PCI config access functions, for the case when we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * find a hose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define NULL_PCI_OP(rw, size, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return PCIBIOS_DEVICE_NOT_FOUND; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct pci_ops null_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .read = null_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .write = null_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * These functions are used early on before PCI scanning is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * and all of the pci_dev and pci_bus structures have been created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static struct pci_bus *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fake_pci_bus(struct pci_controller *hose, int busnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct pci_bus bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pr_err("Can't find hose for PCI bus %d!\n", busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) bus.number = busnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bus.sysdata = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) bus.ops = hose ? hose->ops : &null_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return &bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define EARLY_PCI_OP(rw, size, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int devfn, int offset, type value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) devfn, offset, value); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) EARLY_PCI_OP(read, byte, u8 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) EARLY_PCI_OP(read, word, u16 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) EARLY_PCI_OP(read, dword, u32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) EARLY_PCI_OP(write, byte, u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) EARLY_PCI_OP(write, word, u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) EARLY_PCI_OP(write, dword, u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int early_find_capability(struct pci_controller *hose, int bus, int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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