^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for indirect PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Gabriel Paubert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) volatile void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 cfg_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 bus_no, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (devfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) cfg_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bus_no = (bus->number == hose->first_busno) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) hose->self_busno : bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) reg = offset & 0xfc; /* Only 3 bits for function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Note: the caller has already checked that offset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * suitably aligned and that len is 1, 2 or 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *val = in_8(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *val = in_le16(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *val = in_le32(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) volatile void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 cfg_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 bus_no, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (devfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cfg_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bus_no = (bus->number == hose->first_busno) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hose->self_busno : bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = offset & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* suppress setting of PCI_PRIMARY_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if ((offset == PCI_PRIMARY_BUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (bus->number == hose->first_busno))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val &= 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Workaround for PCI_28 Errata in 440EPx/GRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) offset == PCI_CACHE_LINE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Note: the caller has already checked that offset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * suitably aligned and that len is 1, 2 or 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cfg_data = hose->cfg_data + (offset & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) out_8(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) out_le16(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) out_le32(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct pci_ops indirect_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .read = indirect_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .write = indirect_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) setup_indirect_pci(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) resource_size_t cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) resource_size_t cfg_data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) resource_size_t base = cfg_addr & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __iomem *mbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mbase = ioremap(base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((cfg_data & PAGE_MASK) != base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) hose->ops = &indirect_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hose->indirect_type = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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