Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Unsigned modulo operation for 32 bit integers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Input :	op1 in Reg r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *		op2 in Reg r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Output: op1 mod op2 in Reg r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	.globl	__umodsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	.type __umodsi3, @function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.ent __umodsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __umodsi3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.frame	r1, 0, r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	addik	r1, r1, -12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	swi	r29, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	swi	r30, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	swi	r31, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	beqi	r6, div_by_zero /* div_by_zero - division error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	beqid	r5, result_is_zero /* result is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	addik	r3, r0, 0 /* clear div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	addik	r30, r0, 0 /* clear mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	addik	r29, r0, 32 /* initialize the loop count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* check if r6 and r5 are equal /* if yes, return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	rsub	r18, r5, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	beqi	r18, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* check if (uns)r6 is greater than (uns)r5. in that case, just return r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	xor	r18, r5, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	bgeid	r18, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	addik	r3, r5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	blti	r6, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bri	$lcheckr6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	rsub	r18, r5, r6 /* microblazecmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bgti	r18, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* if r6 [bit 31] is set, then return result as r5-r6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) $lcheckr6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	bgtid	r6, div0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	addik	r3, r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	addik	r18, r0, 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	and	r5, r5, r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	and	r6, r6, r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	brid	return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	rsub	r3, r6, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* first part: try to find the first '1' in the r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) div0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	blti	r5, div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) div1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	add	r5, r5, r5 /* left shift logical r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	bgeid	r5, div1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) div2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* left shift logical r5 get the '1' into the carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	add	r5, r5, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	addc	r3, r3, r3 /* move that bit into the mod register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	rsub	r31, r6, r3 /* try to subtract (r3 a r6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	blti	r31, mod_too_small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	/* move the r31 to mod since the result was positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	or	r3, r0, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	addik	r30, r30, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mod_too_small:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	beqi	r29, loop_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	add	r30, r30, r30 /* shift in the '1' into div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	bri	div2 /* div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) loop_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	bri	return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) div_by_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) result_is_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	or	r3, r0, r0 /* set result to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return_here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* restore values of csrs and that of r3 and the divisor and the dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	lwi	r29, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	lwi	r30, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	lwi	r31, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	rtsd	r15, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	addik	r1, r1, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .size __umodsi3, . - __umodsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .end __umodsi3