Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) * Unsigned divide operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) *	Input :	Divisor in Reg r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) *		Dividend in Reg r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) *	Output: Result in Reg r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	.globl	__udivsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	.type __udivsi3, @function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.ent __udivsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __udivsi3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.frame	r1, 0, r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	addik	r1, r1, -12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	swi	r29, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	swi	r30, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	swi	r31, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	beqi	r6, div_by_zero /* div_by_zero /* division error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	beqid	r5, result_is_zero /* result is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	addik	r30, r0, 0 /* clear mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	addik	r29, r0, 32 /* initialize the loop count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* check if r6 and r5 are equal - if yes, return 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	rsub	r18, r5, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	beqid	r18, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	addik	r3, r0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* check if (uns)r6 is greater than (uns)r5. in that case, just return 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	xor	r18, r5, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bgeid	r18, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	add	r3, r0, r0 /* we would anyways clear r3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	blti	r6, return_here /* r6[bit 31 = 1] hence is greater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	bri	checkr6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	rsub	r18, r6, r5 /* microblazecmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	blti	r18, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* if r6 [bit 31] is set, then return result as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) checkr6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	bgti	r6, div0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	brid	return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	addik	r3, r0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* first part try to find the first '1' in the r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) div0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	blti	r5, div2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) div1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	add	r5, r5, r5 /* left shift logical r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	bgtid	r5, div1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) div2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* left shift logical r5 get the '1' into the carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	add	r5, r5, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	addc	r30, r30, r30 /* move that bit into the mod register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	rsub	r31, r6, r30 /* try to subtract (r30 a r6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	blti	r31, mod_too_small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* move the r31 to mod since the result was positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	or	r30, r0, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	addik	r3, r3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mod_too_small:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	beqi	r29, loop_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	add	r3, r3, r3 /* shift in the '1' into div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	bri	div2 /* div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) loop_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	bri	return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) div_by_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) result_is_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	or	r3, r0, r0 /* set result to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return_here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* restore values of csrs and that of r3 and the divisor and the dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	lwi	r29, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	lwi	r30, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	lwi	r31, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	rtsd	r15, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	addik	r1, r1, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .size __udivsi3, . - __udivsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .end __udivsi3