Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) * modulo operation for 32 bit integers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) *	Input :	op1 in Reg r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) *		op2 in Reg r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) *	Output: op1 mod op2 in Reg r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	.globl	__modsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	.type __modsi3,  @function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.ent __modsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __modsi3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.frame	r1, 0, r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	addik	r1, r1, -16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	swi	r28, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	swi	r29, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	swi	r30, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	swi	r31, r1, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	beqi	r6, div_by_zero /* div_by_zero division error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	beqi	r5, result_is_zero /* result is zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	bgeid	r5, r5_pos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	/* get the sign of the result [ depends only on the first arg] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	add	r28, r5, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	rsubi	r5, r5, 0	 /* make r5 positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) r5_pos:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	bgei	r6, r6_pos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	rsubi	r6, r6, 0	 /* make r6 positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) r6_pos:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	addik	r3, r0, 0 /* clear mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	addik	r30, r0, 0 /* clear div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	addik	r29, r0, 32 /* initialize the loop count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* first part try to find the first '1' in the r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) div1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	add	r5, r5, r5 /* left shift logical r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bgeid	r5, div1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) div2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* left shift logical r5 get the '1' into the carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	add	r5, r5, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	addc	r3, r3, r3 /* move that bit into the mod register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	rsub	r31, r6, r3 /* try to subtract (r30 a r6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	blti	r31, mod_too_small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	/* move the r31 to mod since the result was positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	or	r3, r0, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	addik	r30, r30, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mod_too_small:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	addik	r29, r29, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	beqi	r29, loop_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	add	r30, r30, r30 /* shift in the '1' into div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	bri	div2 /* div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) loop_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	bgei	r28, return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	brid	return_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	rsubi	r3, r3, 0 /* negate the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) div_by_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) result_is_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	or	r3, r0, r0 /* set result to 0 [both mod as well as div are 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return_here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* restore values of csrs and that of r3 and the divisor and the dividend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	lwi	r28, r1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	lwi	r29, r1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	lwi	r30, r1, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	lwi	r31, r1, 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	rtsd	r15, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	addik	r1, r1, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .size __modsi3,  . - __modsi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .end __modsi3