Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012-2013 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static void __iomem *timer_baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static unsigned int freq_div_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static unsigned int timer_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TCSR0	(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TLR0	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TCR0	(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TCSR1	(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TLR1	(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TCR1	(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TCSR_MDT	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TCSR_UDT	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TCSR_GENT	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TCSR_CAPT	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TCSR_ARHT	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TCSR_LOAD	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TCSR_ENIT	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TCSR_ENT	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TCSR_TINT	(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TCSR_PWMA	(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TCSR_ENALL	(1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static unsigned int (*read_fn)(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static void (*write_fn)(u32, void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void timer_write32(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static unsigned int timer_read32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void timer_write32_be(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static unsigned int timer_read32_be(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static inline void xilinx_timer0_stop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		 timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static inline void xilinx_timer0_start_periodic(unsigned long load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (!load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		load_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* loading value to timer reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	write_fn(load_val, timer_baseaddr + TLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* load the initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* see timer data sheet for detail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * !ENALL - don't enable 'em all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * !PWMA - disable pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * TINT - clear interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * ENT- enable timer itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * ENIT - enable interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * !LOAD - clear the bit to let go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * ARHT - auto reload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * !CAPT - no external trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * !GENT - no external signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * UDT - set the timer as down counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * !MDT0 - generate mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		load_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* loading value to timer reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	write_fn(load_val, timer_baseaddr + TLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* load the initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		 timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int xilinx_timer_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 					struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	xilinx_timer0_start_oneshot(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int xilinx_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	xilinx_timer0_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int xilinx_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	pr_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	xilinx_timer0_start_periodic(freq_div_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clock_event_device clockevent_xilinx_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.name			= "xilinx_clockevent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.features		= CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				  CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.shift			= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.rating			= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.set_next_event		= xilinx_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.set_state_shutdown	= xilinx_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.set_state_periodic	= xilinx_timer_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void timer_ack(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static irqreturn_t timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct clock_event_device *evt = &clockevent_xilinx_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	timer_ack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static __init int xilinx_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	clockevent_xilinx_timer.mult =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		div_sc(timer_clock_freq, NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				clockevent_xilinx_timer.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	clockevent_xilinx_timer.max_delta_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	clockevent_xilinx_timer.max_delta_ticks = (u32)~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clockevent_xilinx_timer.min_delta_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		clockevent_delta2ns(1, &clockevent_xilinx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	clockevent_xilinx_timer.min_delta_ticks = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	clockevent_xilinx_timer.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	clockevents_register_device(&clockevent_xilinx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static u64 xilinx_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return read_fn(timer_baseaddr + TCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u64 xilinx_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* reading actual value of timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return (u64)xilinx_clock_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct timecounter xilinx_tc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.cc = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static u64 xilinx_cc_read(const struct cyclecounter *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return xilinx_read(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct cyclecounter xilinx_cc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.read = xilinx_cc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int __init init_xilinx_timecounter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				xilinx_cc.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct clocksource clocksource_microblaze = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.name		= "xilinx_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.rating		= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.read		= xilinx_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.mask		= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int __init xilinx_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ret = clocksource_register_hz(&clocksource_microblaze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				      timer_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		pr_err("failed to register clocksource");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* stop timer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 timer_baseaddr + TCSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* start timer1 - up counting without interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* register timecounter - for ftrace support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return init_xilinx_timecounter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int __init xilinx_timer_init(struct device_node *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	static int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u32 timer_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	timer_baseaddr = of_iomap(timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!timer_baseaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		pr_err("ERROR: invalid timer base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	write_fn = timer_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	read_fn = timer_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		write_fn = timer_write32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		read_fn = timer_read32_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	irq = irq_of_parse_and_map(timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		pr_err("Failed to parse and map irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (timer_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		pr_err("Please enable two timers in HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	pr_info("%pOF: irq=%d\n", timer, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	clk = of_clk_get(timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		pr_err("ERROR: timer CCF input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		/* If there is clock-frequency property than use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		of_property_read_u32(timer, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				    &timer_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		timer_clock_freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (!timer_clock_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		pr_err("ERROR: Using CPU clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		timer_clock_freq = cpuinfo.cpu_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	freq_div_hz = timer_clock_freq / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ret = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			  &clockevent_xilinx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		pr_err("Failed to setup IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	ret = xilinx_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ret = xilinx_clockevent_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		       xilinx_timer_init);