Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * MMU code derived from arch/ppc/kernel/head_4xx.S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *      Initial PowerPC version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *      Rewritten for PReP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *      Low-level exception handers, MMU support, and rewrite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *      PowerPC 8xx modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *    Copyright (c) 1998-1999 TiVo, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *      PowerPC 403GCX modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *      PowerPC 403GCX/405GP modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *    Copyright 2000 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	PPC405 modifications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *      PowerPC 403GCX/405GP modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * 	Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *         	frank_rowand@mvista.com or source@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * 	   	debbie_chu@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/of_fdt.h>		/* for OF_DT_HEADER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/setup.h> /* COMMAND_LINE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) .section .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) .global empty_zero_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) .align 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) empty_zero_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.space	PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) .global swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) swapper_pg_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.space	PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) .section .rodata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) endian_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.word	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	__HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #if CONFIG_KERNEL_BASE_ADDR == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	brai	TOPHYS(real_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.org	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) real_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mts	rmsr, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Disable stack protection from bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	mts	rslr, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	addi	r8, r0, 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	mts	rshr, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * if the msrclr instruction is not enabled. We use this to detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * if the opcode is available, by issuing msrclr and then testing the result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * r8 == 0 - msr instructions are implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * r8 != 0 - msr instructions are not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mfs	r1, rmsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	msrclr	r8, 0 /* clear nothing - just read msr for test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	cmpu	r8, r8, r1 /* r1 must contain msr reg content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* r7 may point to an FDT, or there may be one linked in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)    if it's in r7, we've got to save it away ASAP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)    We ensure r7 points to a valid FDT, just in case the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)    is broken or non-existent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	beqi	r7, no_fdt_arg			/* NULL pointer?  don't copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Does r7 point to a valid FDT? Load HEADER magic number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* Run time Big/Little endian platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	lbui	r11, r0, TOPHYS(endian_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	beqid	r11, big_endian /* DO NOT break delay stop dependency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	lw	r11, r0, r7 /* Big endian load in delay slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	lwr	r11, r0, r7 /* Little endian load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) big_endian:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	rsubi	r11, r11, OF_DT_HEADER	/* Check FDT header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	beqi	r11, _prepare_copy_fdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	or	r7, r0, r0		/* clear R7 when not valid DTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bnei	r11, no_fdt_arg			/* No - get out of here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) _prepare_copy_fdt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	or	r11, r0, r0 /* incremment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ori	r4, r0, TOPHYS(_fdt_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ori	r3, r0, (0x10000 - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) _copy_fdt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	lw	r12, r7, r11 /* r12 = r7 + r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sw	r12, r4, r11 /* addr[r4 + r11] = r12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	addik	r11, r11, 4 /* increment counting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	bgtid	r3, _copy_fdt /* loop for all entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	addik	r3, r3, -4 /* descrement loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) no_fdt_arg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifndef CONFIG_CMDLINE_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * handling command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * copy command line directly to cmd_line placed in data section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	beqid	r5, skip	/* Skip if NULL pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	or	r11, r0, r0		/* incremment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ori	r4, r0, cmd_line	/* load address of command line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	tophys(r4,r4)			/* convert to phys address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ori	r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _copy_command_line:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* r2=r5+r11 - r5 contain pointer to command line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	lbu	r2, r5, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	beqid	r2, skip		/* Skip if no data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	sb	r2, r4, r11		/* addr[r4+r11]= r2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	addik	r11, r11, 1		/* increment counting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	bgtid	r3, _copy_command_line	/* loop for all entries       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	addik	r3, r3, -1		/* decrement loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	addik	r5, r4, 0		/* add new space for command line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tovirt(r5,r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif /* CONFIG_CMDLINE_BOOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef NOT_COMPILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* save bram context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	or	r11, r0, r0				/* incremment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ori	r4, r0, TOPHYS(_bram_load_start)	/* save bram context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ori	r3, r0, (LMB_SIZE - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) _copy_bram:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	lw	r7, r0, r11		/* r7 = r0 + r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	sw	r7, r4, r11		/* addr[r4 + r11] = r7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	addik	r11, r11, 4		/* increment counting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	bgtid	r3, _copy_bram		/* loop for all entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	addik	r3, r3, -4		/* descrement loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* We have to turn on the MMU right away. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Set up the initial MMU state so we can do the first level of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * virtual to physical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	addik	r3, r0, MICROBLAZE_TLB_SIZE -1	/* Invalidate all TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) _invalidate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	mts	rtlbx, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mts	rtlbhi, r0			/* flush: ensure V is clear   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	mts	rtlblo, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	bgtid	r3, _invalidate		/* loop for all entries       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	addik	r3, r3, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Setup the kernel PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mts	rpid,r0			/* Load the kernel PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	bri	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * We should still be executing code at physical address area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * RAM_BASEADDR at this point. However, kernel code is at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * a virtual address. So, set up a TLB mapping to cover this once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * translation is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	addik	r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	tophys(r4,r3)			/* Load the kernel physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* start to do TLB calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	addik	r12, r0, _end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	rsub	r12, r3, r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	addik	r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	or r9, r0, r0 /* TLB0 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	or r10, r0, r0 /* TLB1 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	addik	r11, r12, -0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	bgei	r11, GT16 /* size is greater than 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	addik	r11, r12, -0x0800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	bgei	r11, GT8 /* size is greater than 8MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	addik	r11, r12, -0x0400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	bgei	r11, GT4 /* size is greater than 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* size is less than 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	addik	r11, r12, -0x0200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	bgei	r11, GT2 /* size is greater than 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	addik	r9, r0, 0x0100000 /* TLB0 must be 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	addik	r11, r12, -0x0100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bgei	r11, GT1 /* size is greater than 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* TLB1 is 0 which is setup above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bri tlb_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GT4: /* r11 contains the rest - will be either 1 or 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ori r9, r0, 0x400000 /* TLB0 is 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	bri TLB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GT16: /* TLB0 is 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	addik	r9, r0, 0x1000000 /* means TLB0 is 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TLB1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* must be used r2 because of subtract if failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	addik	r2, r11, -0x0400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bgei	r2, GT20 /* size is greater than 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* size is >16MB and <20MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	addik	r11, r11, -0x0100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	bgei	r11, GT17 /* size is greater than 17MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* kernel is >16MB and < 17MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	addik	r10, r0, 0x0100000 /* means TLB1 is 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	bri tlb_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GT2: /* TLB0 is 0 and TLB1 will be 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GT17: /* TLB1 is 4MB - kernel size <20MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	addik	r10, r0, 0x0400000 /* means TLB1 is 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	bri tlb_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GT8: /* TLB0 is still zero that's why I can use only TLB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GT20: /* TLB1 is 16MB - kernel size >20MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	addik	r10, r0, 0x1000000 /* means TLB1 is 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tlb_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * Configure and load two entries into TLB slots 0 and 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * In case we are pinning TLBs, these are reserved in by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * other TLB functions.  If not reserving, then it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * matter where they are loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	andi	r4,r4,0xfffffc00	/* Mask off the real page number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ori	r4,r4,(TLB_WR | TLB_EX)	/* Set the write and execute bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * TLB0 is always used - check if is not zero (r9 stores TLB0 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * if is use TLB1 value and clear it (r10 stores TLB1 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	bnei	r9, tlb0_not_zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	add	r9, r10, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	add	r10, r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tlb0_not_zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* look at the code below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ori	r30, r0, 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	andi	r29, r9, 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	andi	r29, r9, 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	andi	r29, r9, 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	andi	r3,r3,0xfffffc00	/* Mask off the effective page number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ori	r3,r3,(TLB_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	or	r3, r3, r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Load tlb_skip size value which is index to first unused TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	lwi	r11, r0, TOPHYS(tlb_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	mts     rtlbx,r11		/* TLB slow 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mts	rtlblo,r4		/* Load the data portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mts	rtlbhi,r3		/* Load the tag portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* Increase tlb_skip size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	addik	r11, r11, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	swi	r11, r0, TOPHYS(tlb_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* TLB1 can be zeroes that's why we not setup it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	beqi	r10, jump_over2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* look at the code below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ori	r30, r0, 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	andi	r29, r10, 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	andi	r29, r10, 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	andi	r29, r10, 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	bneid	r29, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	addik	r30, r30, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	addk	r4, r4, r9	/* previous addr + TLB0 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	addk	r3, r3, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	andi	r3,r3,0xfffffc00	/* Mask off the effective page number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ori	r3,r3,(TLB_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	or	r3, r3, r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	lwi	r11, r0, TOPHYS(tlb_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	mts     rtlbx, r11		/* r11 is used from TLB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	mts	rtlblo,r4		/* Load the data portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mts	rtlbhi,r3		/* Load the tag portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Increase tlb_skip size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	addik	r11, r11, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	swi	r11, r0, TOPHYS(tlb_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) jump_over2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * Load a TLB entry for LMB, since we need access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 * the exception vectors, using a 4k real==virtual mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* Use temporary TLB_ID for LMB - clear this temporary mapping later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ori	r11, r0, MICROBLAZE_LMB_TLB_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	mts     rtlbx,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ori	r4,r0,(TLB_WR | TLB_EX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ori	r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mts	rtlblo,r4		/* Load the data portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mts	rtlbhi,r3		/* Load the tag portion of the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 * caches ready to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) turn_on_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ori	r15,r0,start_here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ori	r4,r0,MSR_KERNEL_VMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mts	rmsr,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	rted	r15,0			/* enables MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) start_here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* Initialize small data anchors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	addik	r13, r0, _KERNEL_SDA_BASE_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	addik	r2, r0, _KERNEL_SDA2_BASE_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* Initialize stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	addik	r1, r0, init_thread_union + THREAD_SIZE - 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* Initialize r31 with current task address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	addik	r31, r0, init_task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	addik	r11, r0, machine_early_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	brald	r15, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifndef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	addik	r15, r0, machine_halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	braid	start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 * Initialize the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	bralid	r15, mmu_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* Go back to running unmapped so we can load up new values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 * and change to using our exception vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 * On the MicroBlaze, all we invalidate the used TLB entries to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 * the old 16M byte TLB mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	ori	r15,r0,TOPHYS(kernel_load_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ori	r4,r0,MSR_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	mts	rmsr,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	bri	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	rted	r15,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* Load up the kernel context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) kernel_load_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ori	r5, r0, MICROBLAZE_LMB_TLB_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mts     rtlbx,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	mts	rtlbhi,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	addi	r15, r0, machine_halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	ori	r17, r0, start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ori	r4, r0, MSR_KERNEL_VMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	mts	rmsr, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	rted	r17, 0		/* enable MMU and jump to start_kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #endif /* CONFIG_MMU */