^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pvr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const char family_string[] = CONFIG_XILINX_MICROBLAZE0_FAMILY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const char cpu_ver_string[] = CONFIG_XILINX_MICROBLAZE0_HW_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define err_printk(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) early_printk("ERROR: Microblaze " x "-different for kernel and DTS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ci->use_instr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (fcpu(cpu, "xlnx,use-barrel") ? PVR0_USE_BARREL_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) (fcpu(cpu, "xlnx,use-msr-instr") ? PVR2_USE_MSR_INSTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (fcpu(cpu, "xlnx,use-pcmp-instr") ? PVR2_USE_PCMP_INSTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (fcpu(cpu, "xlnx,use-div") ? PVR0_USE_DIV_MASK : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (CONFIG_XILINX_MICROBLAZE0_USE_BARREL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) i |= PVR0_USE_BARREL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) i |= PVR2_USE_MSR_INSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) i |= PVR2_USE_PCMP_INSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (CONFIG_XILINX_MICROBLAZE0_USE_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) i |= PVR0_USE_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (ci->use_instr != i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) err_printk("BARREL, MSR, PCMP or DIV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ci->use_mult = fcpu(cpu, "xlnx,use-hw-mul");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (ci->use_mult != CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) err_printk("HW_MUL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ci->use_mult =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) (ci->use_mult > 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (PVR2_USE_MUL64_MASK | PVR0_USE_HW_MUL_MASK) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (ci->use_mult == 1 ? PVR0_USE_HW_MUL_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ci->use_fpu = fcpu(cpu, "xlnx,use-fpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ci->use_fpu != CONFIG_XILINX_MICROBLAZE0_USE_FPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) err_printk("HW_FPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ci->use_fpu = (ci->use_fpu > 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (PVR2_USE_FPU2_MASK | PVR0_USE_FPU_MASK) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (ci->use_fpu == 1 ? PVR0_USE_FPU_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ci->use_exc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (fcpu(cpu, "xlnx,unaligned-exceptions") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PVR2_UNALIGNED_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (fcpu(cpu, "xlnx,ill-opcode-exception") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PVR2_ILL_OPCODE_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (fcpu(cpu, "xlnx,iopb-bus-exception") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PVR2_IOPB_BUS_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (fcpu(cpu, "xlnx,dopb-bus-exception") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PVR2_DOPB_BUS_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (fcpu(cpu, "xlnx,div-zero-exception") ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PVR2_DIV_ZERO_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (fcpu(cpu, "xlnx,fpu-exception") ? PVR2_FPU_EXC_MASK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (fcpu(cpu, "xlnx,fsl-exception") ? PVR2_USE_EXTEND_FSL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ci->use_icache = fcpu(cpu, "xlnx,use-icache");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ci->icache_line_length = fcpu(cpu, "xlnx,icache-line-len") << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!ci->icache_line_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (fcpu(cpu, "xlnx,icache-use-fsl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ci->icache_line_length = 4 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ci->icache_line_length = 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ci->icache_size = fcpu(cpu, "i-cache-size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ci->icache_high = fcpu(cpu, "i-cache-highaddr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ci->dcache_line_length = fcpu(cpu, "xlnx,dcache-line-len") << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!ci->dcache_line_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (fcpu(cpu, "xlnx,dcache-use-fsl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ci->dcache_line_length = 4 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ci->dcache_line_length = 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ci->dcache_size = fcpu(cpu, "d-cache-size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ci->dcache_wb = fcpu(cpu, "xlnx,dcache-use-writeback");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ci->use_iopb = fcpu(cpu, "xlnx,i-opb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ci->use_dlmb = fcpu(cpu, "xlnx,d-lmb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ci->use_ilmb = fcpu(cpu, "xlnx,i-lmb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ci->num_fsl = fcpu(cpu, "xlnx,fsl-links");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ci->irq_edge = fcpu(cpu, "xlnx,interrupt-is-edge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ci->irq_positive = fcpu(cpu, "xlnx,edge-is-positive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ci->area_optimised = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ci->hw_debug = fcpu(cpu, "xlnx,debug-enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ci->num_pc_brk = fcpu(cpu, "xlnx,number-of-pc-brk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ci->num_rd_brk = fcpu(cpu, "xlnx,number-of-rd-addr-brk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ci->num_wr_brk = fcpu(cpu, "xlnx,number-of-wr-addr-brk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ci->pvr_user1 = fcpu(cpu, "xlnx,pvr-user1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ci->mmu = fcpu(cpu, "xlnx,use-mmu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ci->mmu_privins = fcpu(cpu, "xlnx,mmu-privileged-instr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ci->endian = fcpu(cpu, "xlnx,endianness");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ci->ver_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ci->fpga_family_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Do various fixups based on CPU version and FPGA family strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Resolved the CPU version code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (strcmp(cpu_ver_lookup[i].s, cpu_ver_string) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ci->ver_code = cpu_ver_lookup[i].k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Resolved the fpga family code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0; family_string_lookup[i].s != NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (strcmp(family_string_lookup[i].s, family_string) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ci->fpga_family_code = family_string_lookup[i].k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* FIXME - mb3 and spartan2 do not exist in PVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* This is mb3 and on a non Spartan2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ci->ver_code == 0x20 && ci->fpga_family_code != 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Hardware Multiplier in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ci->use_mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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