^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Support for MicroBlaze PVR (processor version register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pvr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Helper macro to map between fields in our struct cpuinfo, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * the PVR macros in pvr.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CI(c, p) { ci->c = PVR_##p(pvr); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define err_printk(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pr_err("ERROR: Microblaze " x "-different for PVR and DTS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pvr_s pvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 temp; /* for saving temp value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) get_pvr(&pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CI(ver_code, VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (!ci->ver_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ci->use_instr != temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) err_printk("BARREL, MSR, PCMP or DIV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ci->use_instr = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (ci->use_mult != temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) err_printk("HW_MUL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ci->use_mult = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ci->use_fpu != temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) err_printk("HW_FPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ci->use_fpu = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PVR_UNALIGNED_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PVR_ILL_OPCODE_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PVR_IOPB_BUS_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PVR_DOPB_BUS_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PVR_DIV_ZERO_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PVR_FPU_EXCEPTION(pvr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PVR_FSL_EXCEPTION(pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CI(pvr_user1, USER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CI(pvr_user2, USER2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CI(mmu, USE_MMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CI(mmu_privins, MMU_PRIVINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CI(endian, ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CI(use_icache, USE_ICACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CI(icache_write, ICACHE_ALLOW_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) CI(icache_size, ICACHE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CI(icache_base, ICACHE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CI(icache_high, ICACHE_HIGHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CI(use_dcache, USE_DCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CI(dcache_write, DCACHE_ALLOW_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CI(dcache_size, DCACHE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CI(dcache_base, DCACHE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CI(dcache_high, DCACHE_HIGHADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) temp = PVR_DCACHE_USE_WRITEBACK(pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ci->dcache_wb != temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) err_printk("DCACHE WB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ci->dcache_wb = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CI(use_dopb, D_OPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CI(use_iopb, I_OPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CI(use_dlmb, D_LMB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CI(use_ilmb, I_LMB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CI(num_fsl, FSL_LINKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CI(irq_edge, INTERRUPT_IS_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CI(irq_positive, EDGE_IS_POSITIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CI(area_optimised, AREA_OPTIMISED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CI(hw_debug, DEBUG_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CI(num_pc_brk, NUMBER_OF_PC_BRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CI(fpga_family_code, TARGET_FAMILY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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