^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Cache control for MicroBlaze cache memories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2009 John Williams <john.williams@petalogix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpuinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/pvr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static inline void __enable_icache_msr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __asm__ __volatile__ (" msrset r0, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) : : "i" (MSR_ICE) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline void __disable_icache_msr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __asm__ __volatile__ (" msrclr r0, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) : : "i" (MSR_ICE) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline void __enable_dcache_msr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __asm__ __volatile__ (" msrset r0, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) : : "i" (MSR_DCE) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline void __disable_dcache_msr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __asm__ __volatile__ (" msrclr r0, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "nop; " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) : : "i" (MSR_DCE) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void __enable_icache_nomsr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __asm__ __volatile__ (" mfs r12, rmsr;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "ori r12, r12, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "mts rmsr, r12;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) : : "i" (MSR_ICE) : "memory", "r12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void __disable_icache_nomsr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __asm__ __volatile__ (" mfs r12, rmsr;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "andi r12, r12, ~%0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "mts rmsr, r12;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) : : "i" (MSR_ICE) : "memory", "r12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void __enable_dcache_nomsr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __asm__ __volatile__ (" mfs r12, rmsr;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "ori r12, r12, %0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "mts rmsr, r12;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) : : "i" (MSR_DCE) : "memory", "r12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline void __disable_dcache_nomsr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __asm__ __volatile__ (" mfs r12, rmsr;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "andi r12, r12, ~%0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "mts rmsr, r12;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "nop;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) : : "i" (MSR_DCE) : "memory", "r12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Helper macro for computing the limits of cache range loops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * End address can be unaligned which is OK for C implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * ASM implementation align it in ASM macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int align = ~(cache_line_length - 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (start < UINT_MAX - cache_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) end = min(start + cache_size, end); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) start &= align; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Helper macro to loop over the specified cache_size/line_length and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * execute 'op' on that cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CACHE_ALL_LOOP(cache_size, line_length, op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int len = cache_size - line_length; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int step = -line_length; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) WARN_ON(step >= 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __asm__ __volatile__ (" 1: " #op " %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "bgtid %0, 1b;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "addk %0, %0, %1;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) : : "r" (len), "r" (step) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Used for wdc.flush/clear which can use rB for offset which is not possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * to use for simple wdc or wic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * start address is cache aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * end address is not aligned, if end is aligned then I have to subtract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * cacheline length because I can't flush/invalidate the next cacheline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * If is not, I align it because I will flush/invalidate whole line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CACHE_RANGE_LOOP_2(start, end, line_length, op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int step = -line_length; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int align = ~(line_length - 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int count; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) end = ((end & align) == end) ? end - line_length : end & align; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) count = end - start; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WARN_ON(count < 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __asm__ __volatile__ (" 1: " #op " %0, %1;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "bgtid %1, 1b;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "addk %1, %1, %2;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) : : "r" (start), "r" (count), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "r" (step) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* It is used only first parameter for OP - for wic, wdc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CACHE_RANGE_LOOP_1(start, end, line_length, op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int volatile temp = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int align = ~(line_length - 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) end = ((end & align) == end) ? end - line_length : end & align; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) WARN_ON(end < start); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __asm__ __volatile__ (" 1: " #op " %1, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "cmpu %0, %1, %2;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "bgtid %0, 1b;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "addk %1, %1, %3;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) : : "r" (temp), "r" (start), "r" (end), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "r" (line_length) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cpuinfo.icache_line_length, cpuinfo.icache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __disable_icache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (i = start; i < end; i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __enable_icache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void __flush_icache_range_nomsr_irq(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpuinfo.icache_line_length, cpuinfo.icache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __disable_icache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = start; i < end; i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __enable_icache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void __flush_icache_range_noirq(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cpuinfo.icache_line_length, cpuinfo.icache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) for (i = start; i < end; i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void __flush_icache_all_msr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __disable_icache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < cpuinfo.icache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __enable_icache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void __flush_icache_all_nomsr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __disable_icache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (i = 0; i < cpuinfo.icache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __enable_icache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void __flush_icache_all_noirq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CACHE_ALL_LOOP(cpuinfo.icache_size, cpuinfo.icache_line_length, wic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) for (i = 0; i < cpuinfo.icache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) i += cpuinfo.icache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __asm__ __volatile__ ("wic %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void __invalidate_dcache_all_msr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __disable_dcache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; i < cpuinfo.dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __enable_dcache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void __invalidate_dcache_all_nomsr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __disable_dcache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < cpuinfo.dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __enable_dcache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void __invalidate_dcache_all_noirq_wt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (i = 0; i < cpuinfo.dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * FIXME It is blindly invalidation as is expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * but can't be called on noMMU in microblaze_cache_init below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * MS: noMMU kernel won't boot if simple wdc is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * The reason should be that there are discared data which kernel needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void __invalidate_dcache_all_wb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (i = 0; i < cpuinfo.dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void __invalidate_dcache_range_wb(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cpuinfo.dcache_line_length, cpuinfo.dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = start; i < end; i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __asm__ __volatile__ ("wdc.clear %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void __invalidate_dcache_range_nomsr_wt(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cpuinfo.dcache_line_length, cpuinfo.dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for (i = start; i < end; i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void __invalidate_dcache_range_msr_irq_wt(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cpuinfo.dcache_line_length, cpuinfo.dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __disable_dcache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) for (i = start; i < end; i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __enable_dcache_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void __invalidate_dcache_range_nomsr_irq(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cpuinfo.dcache_line_length, cpuinfo.dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __disable_dcache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (i = start; i < end; i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __asm__ __volatile__ ("wdc %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __enable_dcache_nomsr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void __flush_dcache_all_wb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CACHE_ALL_LOOP(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) wdc.flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (i = 0; i < cpuinfo.dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __asm__ __volatile__ ("wdc.flush %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void __flush_dcache_range_wb(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #ifndef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pr_debug("%s: start 0x%x, end 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (unsigned int)start, (unsigned int) end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) CACHE_LOOP_LIMITS(start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cpuinfo.dcache_line_length, cpuinfo.dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #ifdef ASM_LOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (i = start; i < end; i += cpuinfo.dcache_line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __asm__ __volatile__ ("wdc.flush %0, r0;" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) : : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* struct for wb caches and for wt caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct scache *mbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* new wb cache model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct scache wb_msr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .ie = __enable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .id = __disable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .ifl = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .iflr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .iin = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .iinr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .de = __enable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .dd = __disable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .dfl = __flush_dcache_all_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .dflr = __flush_dcache_range_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .din = __invalidate_dcache_all_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .dinr = __invalidate_dcache_range_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* There is only difference in ie, id, de, dd functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct scache wb_nomsr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .ie = __enable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .id = __disable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .ifl = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .iflr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .iin = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .iinr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .de = __enable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .dd = __disable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .dfl = __flush_dcache_all_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .dflr = __flush_dcache_range_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .din = __invalidate_dcache_all_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .dinr = __invalidate_dcache_range_wb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Old wt cache model with disabling irq and turn off cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct scache wt_msr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ie = __enable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .id = __disable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .ifl = __flush_icache_all_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .iflr = __flush_icache_range_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .iin = __flush_icache_all_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .iinr = __flush_icache_range_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .de = __enable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .dd = __disable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .dfl = __invalidate_dcache_all_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .dflr = __invalidate_dcache_range_msr_irq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .din = __invalidate_dcache_all_msr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .dinr = __invalidate_dcache_range_msr_irq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct scache wt_nomsr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ie = __enable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .id = __disable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ifl = __flush_icache_all_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .iflr = __flush_icache_range_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .iin = __flush_icache_all_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .iinr = __flush_icache_range_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .de = __enable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .dd = __disable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .dfl = __invalidate_dcache_all_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .dflr = __invalidate_dcache_range_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .din = __invalidate_dcache_all_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .dinr = __invalidate_dcache_range_nomsr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* New wt cache model for newer Microblaze versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct scache wt_msr_noirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ie = __enable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .id = __disable_icache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .ifl = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .iflr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .iin = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .iinr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .de = __enable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .dd = __disable_dcache_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .dfl = __invalidate_dcache_all_noirq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .dflr = __invalidate_dcache_range_nomsr_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .din = __invalidate_dcache_all_noirq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .dinr = __invalidate_dcache_range_nomsr_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct scache wt_nomsr_noirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .ie = __enable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .id = __disable_icache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .ifl = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .iflr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .iin = __flush_icache_all_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .iinr = __flush_icache_range_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .de = __enable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .dd = __disable_dcache_nomsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .dfl = __invalidate_dcache_all_noirq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .dflr = __invalidate_dcache_range_nomsr_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .din = __invalidate_dcache_all_noirq_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .dinr = __invalidate_dcache_range_nomsr_wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* CPU version code for 7.20.c - see arch/microblaze/kernel/cpu/cpuinfo.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define CPUVER_7_20_A 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CPUVER_7_20_D 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void microblaze_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (cpuinfo.dcache_wb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pr_info("wb_msr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mbc = (struct scache *)&wb_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (cpuinfo.ver_code <= CPUVER_7_20_D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* MS: problem with signal handling - hw bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pr_info("WB won't work properly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (cpuinfo.ver_code >= CPUVER_7_20_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pr_info("wt_msr_noirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mbc = (struct scache *)&wt_msr_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pr_info("wt_msr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mbc = (struct scache *)&wt_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (cpuinfo.dcache_wb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pr_info("wb_nomsr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) mbc = (struct scache *)&wb_nomsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (cpuinfo.ver_code <= CPUVER_7_20_D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* MS: problem with signal handling - hw bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pr_info("WB won't work properly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (cpuinfo.ver_code >= CPUVER_7_20_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pr_info("wt_nomsr_noirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mbc = (struct scache *)&wt_nomsr_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pr_info("wt_nomsr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mbc = (struct scache *)&wt_nomsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * FIXME Invalidation is done in U-BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * WT cache: Data is already written to main memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * WB cache: Discard data on noMMU which caused that kernel doesn't boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* invalidate_dcache(); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) enable_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) invalidate_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) enable_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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