Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2008-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_MICROBLAZE_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_MICROBLAZE_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MSR_BE	(1<<0) /* 0x001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MSR_IE	(1<<1) /* 0x002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MSR_C	(1<<2) /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MSR_BIP	(1<<3) /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MSR_FSL	(1<<4) /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MSR_ICE	(1<<5) /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MSR_DZ	(1<<6) /* 0x040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MSR_DCE	(1<<7) /* 0x080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MSR_EE	(1<<8) /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSR_EIP	(1<<9) /* 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MSR_CC	(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Floating Point Status Register (FSR) Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FSR_IO		(1<<4) /* Invalid operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FSR_DZ		(1<<3) /* Divide-by-zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSR_OF		(1<<2) /* Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSR_UF		(1<<1) /* Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSR_DO		(1<<0) /* Denormalized operand error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Machine State Register (MSR) Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define MSR_UM		(1<<11) /* User Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define MSR_UMS	(1<<12) /* User Mode Save */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define MSR_VM		(1<<13) /* Virtual Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define MSR_VMS	(1<<14) /* Virtual Mode Save */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define MSR_KERNEL	(MSR_EE | MSR_VM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* # define MSR_USER	(MSR_KERNEL | MSR_UM | MSR_IE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define MSR_KERNEL_VMS	(MSR_EE | MSR_VMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* # define MSR_USER_VMS	(MSR_KERNEL_VMS | MSR_UMS | MSR_IE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Exception State Register (ESR) Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define	  ESR_DIZ	(1<<11) /* Zone Protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define	  ESR_S		(1<<10) /* Store instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* _ASM_MICROBLAZE_REGISTERS_H */