Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Support for the MicroBlaze PVR (Processor Version Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2007 - 2011 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _ASM_MICROBLAZE_PVR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _ASM_MICROBLAZE_PVR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PVR_MSR_BIT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct pvr_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	unsigned pvr[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* The following taken from Xilinx's standalone BSP pvr.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Basic PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PVR0_PVR_FULL_MASK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PVR0_USE_BARREL_MASK		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PVR0_USE_DIV_MASK		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PVR0_USE_HW_MUL_MASK		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PVR0_USE_FPU_MASK		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PVR0_USE_EXC_MASK		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PVR0_USE_ICACHE_MASK		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PVR0_USE_DCACHE_MASK		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PVR0_USE_MMU			0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PVR0_USE_BTC			0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PVR0_ENDI			0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PVR0_VERSION_MASK		0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PVR0_USER1_MASK			0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* User 2 PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PVR1_USER2_MASK			0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Configuration PVR masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PVR2_D_OPB_MASK			0x80000000 /* or AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PVR2_D_LMB_MASK			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PVR2_I_OPB_MASK			0x20000000 /* or AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PVR2_I_LMB_MASK			0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PVR2_INTERRUPT_IS_EDGE_MASK	0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PVR2_EDGE_IS_POSITIVE_MASK	0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PVR2_D_PLB_MASK			0x02000000 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PVR2_I_PLB_MASK			0x01000000 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PVR2_INTERCONNECT		0x00800000 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PVR2_USE_EXTEND_FSL		0x00080000 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PVR2_USE_FSL_EXC		0x00040000 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PVR2_USE_MSR_INSTR		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PVR2_USE_PCMP_INSTR		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PVR2_AREA_OPTIMISED		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PVR2_USE_BARREL_MASK		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PVR2_USE_DIV_MASK		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PVR2_USE_HW_MUL_MASK		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PVR2_USE_FPU_MASK		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PVR2_USE_MUL64_MASK		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PVR2_USE_FPU2_MASK		0x00000200 /* new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PVR2_USE_IPLBEXC 		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PVR2_USE_DPLBEXC		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PVR2_OPCODE_0x0_ILL_MASK	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PVR2_UNALIGNED_EXC_MASK		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PVR2_ILL_OPCODE_EXC_MASK	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PVR2_IOPB_BUS_EXC_MASK		0x00000008 /* or AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PVR2_DOPB_BUS_EXC_MASK		0x00000004 /* or AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PVR2_DIV_ZERO_EXC_MASK		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PVR2_FPU_EXC_MASK		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Debug and exception PVR masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PVR3_DEBUG_ENABLED_MASK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PVR3_NUMBER_OF_PC_BRK_MASK	0x1E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK	0x00380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK	0x0000E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PVR3_FSL_LINKS_MASK		0x00000380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* ICache config PVR masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PVR4_USE_ICACHE_MASK		0x80000000 /* ICU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PVR4_ICACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* ICTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PVR4_ICACHE_ALLOW_WR_MASK	0x01000000 /* ICW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PVR4_ICACHE_LINE_LEN_MASK	0x00E00000 /* ICLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PVR4_ICACHE_BYTE_SIZE_MASK	0x001F0000 /* ICBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PVR4_ICACHE_ALWAYS_USED		0x00008000 /* IAU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PVR4_ICACHE_INTERFACE		0x00002000 /* ICI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* DCache config PVR masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PVR5_USE_DCACHE_MASK		0x80000000 /* DCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PVR5_DCACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* DCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PVR5_DCACHE_ALLOW_WR_MASK	0x01000000 /* DCW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PVR5_DCACHE_LINE_LEN_MASK	0x00E00000 /* DCLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PVR5_DCACHE_BYTE_SIZE_MASK	0x001F0000 /* DCBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PVR5_DCACHE_ALWAYS_USED		0x00008000 /* DAU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PVR5_DCACHE_USE_WRITEBACK	0x00004000 /* DWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PVR5_DCACHE_INTERFACE		0x00002000 /* DCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* ICache base address PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PVR6_ICACHE_BASEADDR_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* ICache high address PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PVR7_ICACHE_HIGHADDR_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* DCache base address PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PVR8_DCACHE_BASEADDR_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* DCache high address PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PVR9_DCACHE_HIGHADDR_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Target family PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PVR10_TARGET_FAMILY_MASK	0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* MMU description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PVR11_USE_MMU			0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PVR11_MMU_ITLB_SIZE		0x38000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PVR11_MMU_DTLB_SIZE		0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PVR11_MMU_TLB_ACCESS		0x00C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PVR11_MMU_ZONES			0x003C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PVR11_MMU_PRIVINS		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* MSR Reset value PVR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PVR11_MSR_RESET_VALUE_MASK	0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* PVR access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PVR_IS_FULL(_pvr)	(_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PVR_USE_BARREL(_pvr)	(_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PVR_USE_DIV(_pvr)	(_pvr.pvr[0] & PVR0_USE_DIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PVR_USE_HW_MUL(_pvr)	(_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PVR_USE_FPU(_pvr)	(_pvr.pvr[0] & PVR0_USE_FPU_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PVR_USE_FPU2(_pvr)	(_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PVR_USE_ICACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PVR_USE_DCACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PVR_VERSION(_pvr)	((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PVR_USER1(_pvr)		(_pvr.pvr[0] & PVR0_USER1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PVR_USER2(_pvr)		(_pvr.pvr[1] & PVR1_USER2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PVR_D_OPB(_pvr)		(_pvr.pvr[2] & PVR2_D_OPB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PVR_D_LMB(_pvr)		(_pvr.pvr[2] & PVR2_D_LMB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PVR_I_OPB(_pvr)		(_pvr.pvr[2] & PVR2_I_OPB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PVR_I_LMB(_pvr)		(_pvr.pvr[2] & PVR2_I_LMB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PVR_INTERRUPT_IS_EDGE(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			(_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PVR_EDGE_IS_POSITIVE(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			(_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PVR_USE_MSR_INSTR(_pvr)		(_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PVR_USE_PCMP_INSTR(_pvr)	(_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PVR_AREA_OPTIMISED(_pvr)	(_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PVR_USE_MUL64(_pvr)		(_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			(_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PVR_UNALIGNED_EXCEPTION(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			(_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			(_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PVR_IOPB_BUS_EXCEPTION(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			(_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PVR_DOPB_BUS_EXCEPTION(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			(_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PVR_DIV_ZERO_EXCEPTION(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			(_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PVR_FPU_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PVR_FSL_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PVR_DEBUG_ENABLED(_pvr)		(_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PVR_NUMBER_OF_PC_BRK(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PVR_FSL_LINKS(_pvr)	((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PVR_ICACHE_USE_FSL(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		(_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PVR_ICACHE_ALLOW_WR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		(_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PVR_ICACHE_LINE_LEN(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PVR_ICACHE_BYTE_SIZE(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PVR_DCACHE_USE_FSL(_pvr)	(_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PVR_DCACHE_ALLOW_WR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			(_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* FIXME two shifts on one line needs any comment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PVR_DCACHE_LINE_LEN(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PVR_DCACHE_BYTE_SIZE(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PVR_DCACHE_USE_WRITEBACK(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PVR_ICACHE_BASEADDR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			(_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PVR_ICACHE_HIGHADDR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			(_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PVR_DCACHE_BASEADDR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			(_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PVR_DCACHE_HIGHADDR(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			(_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PVR_TARGET_FAMILY(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PVR_MSR_RESET_VALUE(_pvr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			(_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* mmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PVR_USE_MMU(_pvr)		((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PVR_MMU_ITLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PVR_MMU_DTLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PVR_MMU_TLB_ACCESS(_pvr)	(_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PVR_MMU_ZONES(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ZONES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PVR_MMU_PRIVINS(pvr)		(pvr.pvr[11] & PVR11_MMU_PRIVINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PVR_ENDIAN(_pvr)	(_pvr.pvr[0] & PVR0_ENDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int cpu_has_pvr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void get_pvr(struct pvr_s *pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif /* _ASM_MICROBLAZE_PVR_H */