^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008-2009 PetaLogix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Atmark Techno, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_MICROBLAZE_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_MICROBLAZE_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern int mem_init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pgd_present(pgd) (1) /* pages are always present on non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define pgd_none(pgd) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pgd_bad(pgd) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define pgd_clear(pgdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define pgprot_noncached(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pgprot_writecombine pgprot_noncached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define pgprot_device pgprot_noncached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __swp_type(x) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __swp_offset(x) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZERO_PAGE(vaddr) ({ BUG(); NULL; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define swapper_pg_dir ((pgd_t *) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define arch_enter_lazy_cpu_mode() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define pgprot_noncached_wc(prot) prot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * All 32bit addresses are effectively valid for vmalloc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Sort of meaningless for non-VM targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VMALLOC_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VMALLOC_END 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm-generic/pgtable-nopmd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <asm/processor.h> /* For TASK_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FIRST_USER_ADDRESS 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern unsigned long va_to_phys(unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern pte_t *va_to_pte(unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The following only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Undefined behaviour if not..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Start and end of the vmalloc area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Make sure to map the vmalloc area above the pinned kernel memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) of 32Mb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VMALLOC_END ioremap_bot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Macro to mark a page protection value as "uncacheable".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) _PAGE_WRITETHRU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define pgprot_noncached(prot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) _PAGE_NO_CACHE | _PAGE_GUARDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define pgprot_noncached_wc(prot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) _PAGE_NO_CACHE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * table containing PTEs, together with a set of 16 segment registers, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * define the virtual to physical address mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * We use the hash table as an extended TLB, i.e. a cache of currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * active mappings. We maintain a two-level page table tree, much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * like that used by the i386, for the sake of the Linux memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * management code. Low-level assembler code in hashtable.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * (procedure hash_page) is responsible for extracting ptes from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * tree and putting them into the hash table when necessary, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * updating the accessed and modified bits in the page table tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * instruction and data sides share a unified, 64-entry, semi-associative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * TLB which is maintained totally under software control. In addition, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * TLB which serves as a first level to the shared TLB. These two TLBs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The normal case is that PTEs are 32-bits and we have a 1-page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PGDIR_SHIFT determines what a top-level page table entry can map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PGDIR_MASK (~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * entries per page directory level: our page-table tree is two-level, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * we don't really have any PMD directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PTRS_PER_PTE (1 << PTE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PTRS_PER_PMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FIRST_USER_PGD_NR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define pte_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __FILE__, __LINE__, pte_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define pgd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __FILE__, __LINE__, pgd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Bits in a linux-style PTE. These match the bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * (hardware-defined) PTE as closely as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* There are several potential gotchas here. The hardware TLBLO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * field looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * RPN..................... 0 0 EX WR ZSEL....... W I M G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Where possible we make the Linux PTE bits match up with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * support down to 1k pages), this is done in the TLBMiss exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * - We use only zones 0 (for kernel pages) and 1 (for user pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * zone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - PRESENT *must* be in the bottom two bits because swap cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * entries use the top 30 bits. Because 4xx doesn't support SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * is cleared in the TLB miss handler before the TLB entry is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * - All other bits of the PTE are loaded into TLBLO without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * software PTE bits. We actually use bits 21, 24, 25, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * PRESENT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Definitions for MicroBlaze. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define _PAGE_RW 0x040 /* software: Writes permitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define _PAGE_DIRTY 0x080 /* software: dirty page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define _PMD_PRESENT PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Some bits are unused...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifndef _PAGE_HASHPTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define _PAGE_HASHPTE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #ifndef _PTE_NONE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define _PTE_NONE_MASK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifndef _PAGE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define _PAGE_SHARED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifndef _PAGE_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define _PAGE_EXEC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * to have it in the Linux PTE, and in fact the bit could be reused for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * another purpose. -- paulus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define _PAGE_KERNEL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PAGE_NONE __pgprot(_PAGE_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PAGE_SHARED_X \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * We consider execute permission the same as read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Also, write permissions imply read permissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define __P000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define __P001 PAGE_READONLY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define __P010 PAGE_COPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define __P011 PAGE_COPY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define __P100 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define __P101 PAGE_READONLY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define __P110 PAGE_COPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define __P111 PAGE_COPY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define __S000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define __S001 PAGE_READONLY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define __S010 PAGE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define __S011 PAGE_SHARED_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define __S100 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define __S101 PAGE_READONLY_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define __S110 PAGE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define __S111 PAGE_SHARED_X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * ZERO_PAGE is a global shared page that is always zero: used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * for zero-mapped memory areas etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extern unsigned long empty_zero_page[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define pte_clear(mm, addr, ptep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define pmd_none(pmd) (!pmd_val(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define pte_page(x) (mem_map + (unsigned long) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ((pte_val(x) - memory_start) >> PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PFN_SHIFT_OFFSET (PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define pfn_pte(pfn, prot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * The following only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Undefined behaviour if not..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static inline pte_t pte_rdprotect(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { pte_val(pte) &= ~_PAGE_USER; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline pte_t pte_wrprotect(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static inline pte_t pte_exprotect(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline pte_t pte_mkclean(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline pte_t pte_mkold(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline pte_t pte_mkread(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { pte_val(pte) |= _PAGE_USER; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline pte_t pte_mkexec(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline pte_t pte_mkwrite(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { pte_val(pte) |= _PAGE_RW; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline pte_t pte_mkdirty(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static inline pte_t pte_mkyoung(pte_t pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Conversion functions: convert a page and protection to a page entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * and a page entry and page directory to the page they refer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pte_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pte_val(pte) = physpage | pgprot_val(pgprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define mk_pte(page, pgprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pte_t pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pgprot_val(pgprot); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Atomic PTE updates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * pte_update clears and sets bit atomically, and returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * the old pte value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline unsigned long pte_update(pte_t *p, unsigned long clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned long flags, old, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) raw_local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __asm__ __volatile__( "lw %0, %2, r0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "andn %1, %0, %3 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "or %1, %1, %4 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "sw %1, %2, r0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) : "=&r" (old), "=&r" (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) raw_local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * set_pte stores a linux PTE into the linux page table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline void set_pte(struct mm_struct *mm, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pte_t *ptep, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *ptep = pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pte_t *ptep, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *ptep = pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long address, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return (pte_update(ptep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*static inline void ptep_set_wrprotect(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline void ptep_mkdirty(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pte_update(ptep, 0, _PAGE_DIRTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Convert pmd entry to page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* our pmd entry is an effective address of pte table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* returns effective address of the pmd entry*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline unsigned long pmd_page_vaddr(pmd_t pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ((unsigned long) (pmd_val(pmd) & PAGE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* returns struct *page of the pmd entry*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Find an entry in the third-level page table.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Encode and decode a swap entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Note that the bits we use in a PTE for representing a swap entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * (if used). -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define __swp_type(entry) ((entry).val & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define __swp_offset(entry) ((entry).val >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define __swp_entry(type, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ((swp_entry_t) { (type) | ((offset) << 6) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) extern unsigned long iopa(unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Values for nocacheflag and cmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* These are not used by the APUS kernel_map, but prevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * compilation errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define IOMAP_FULL_CACHING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define IOMAP_NOCACHE_SER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define IOMAP_NOCACHE_NONSER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define IOMAP_NO_COPYBACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void do_page_fault(struct pt_regs *regs, unsigned long address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned long error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void mapin_ram(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int map_page(unsigned long va, phys_addr_t pa, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) extern int mem_init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) asmlinkage void __init mmu_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) void __init *early_get_page(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) extern unsigned long ioremap_bot, ioremap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void setup_memory(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif /* _ASM_MICROBLAZE_PGTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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